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/**
* @file
*
* ALIB PSPP config
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
* @e \$Revision: 49214 $ @e \$Date: 2011-03-19 07:05:12 +0800 (Sat, 19 Mar 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*
*/
#ifndef _PCIEALIBCONFIG_H_
#define _PCIEALIBCONFIG_H_
//#define PCIE_PHY_LANE_POWER_GATE_SUPPORT
// #define PCIE_DISABLE_UNUSED_LANES_ON_ACTIVE_LINK
#define DEF_OFFSET_START_CORE_LANE 2
#define DEF_OFFSET_END_CORE_LANE 3
#define DEF_OFFSET_START_PHY_LANE 0
#define DEF_OFFSET_END_PHY_LANE 1
#define DEF_OFFSET_PORT_ID 4
#define DEF_OFFSET_WRAPPER_ID 5
#define DEF_OFFSET_LINK_HOTPLUG 7
#define DEF_OFFSET_GEN2_CAP 8
#define DEF_BASIC_HOTPLUG 1
#define DEF_PSPP_POLICY_START 1
#define DEF_PSPP_POLICY_STOP 0
#define DEF_PSPP_POLICY_PERFORMANCE 1
#define DEF_PSPP_POLICY_BALANCEHIGH 2
#define DEF_PSPP_POLICY_BALANCELOW 3
#define DEF_PSPP_POLICY_POWERSAVING 4
#define DEF_PSPP_STATE_AC 0
#define DEF_PSPP_STATE_DC 1
#define DEF_TRAINING_STATE_COMPLETE 0
#define DEF_TRAINING_STATE_DETECT_PRESENCE 1
#define DEF_TRAINING_STATE_PRESENCE_DETECTED 2
#define DEF_TRAINING_GEN2_WORKAROUND 3
#define DEF_TRAINING_STATE_NOT_PRESENT 4
#define DEF_TRAINING_DEVICE_PRESENT 5
#define DEF_TRAINING_STATE_RELEASE_TRAINING 6
#define DEF_TRAINING_STATE_REQUEST_RESET 7
#define DEF_TRAINING_STATE_EXIT 8
#define DEF_LINK_SPEED_GEN1 1
#define DEF_LINK_SPEED_GEN2 2
#define DEF_HOTPLUG_STATUS_DEVICE_NOT_PRESENT 0
#define DEF_HOTPLUG_STATUS_DEVICE_PRESENT 1
#define DEF_PORT_NOT_ALLOCATED 0
#define DEF_PORT_ALLOCATED 1
#define DEF_PCIE_LANE_POWERON 1
#define DEF_PCIE_LANE_POWEROFF 0
#define DEF_PCIE_LANE_POWEROFFUNUSED 2
#define DEF_SCARTCH_PSPP_START_OFFSET 0
#define DEF_SCARTCH_PSPP_POLICY_OFFSET 1
#define DEF_SCARTCH_PSPP_ACDC_OFFSET 5
#define DEF_SCARTCH_PSPP_ACDC_OVR_OFFSET 6
#define DEF_SCARTCH_PSPP_REQ_OFFSET 16
#define DEF_LINKWIDTH_ACTIVE 0
#define DEF_LINKWIDTH_MAX_PHY 1
#define TRUE 1
#define FALSE 0
#endif
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