aboutsummaryrefslogtreecommitdiff
path: root/src/southbridge/sis/sis966/sis761.c
blob: 090e6e9e210a7b70807e7aa237d94ddd0d6b31c4 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
/*
 * This file is part of the coreboot project.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 *
 * Turn off machine check triggers when reading
 * pci space where there are no devices.
 * This is necessary when scaning the bus for
 * devices which is done by the kernel
 *
 * written in 2003 by Eric Biederman
 *
 *  - Athlon64 workarounds by Stefan Reinauer
 *  - "reset once" logic by Yinghai Lu
 * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
 * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
 *
 */

#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <part/hard_reset.h>
#include <pc80/mc146818rtc.h>
#include <bitops.h>
#include <cpu/amd/model_fxx_rev.h>

//#include "amdk8.h"

#include <arch/io.h>

/**
 * @brief Read resources for AGP aperture
 *
 * @param
 *
 * There is only one AGP aperture resource needed. The resoruce is added to
 * the northbridge of BSP.
 *
 * The same trick can be used to augment legacy VGA resources which can
 * be detect by generic pci reousrce allocator for VGA devices.
 * BAD: it is more tricky than I think, the resource allocation code is
 * implemented in a way to NOT DOING legacy VGA resource allcation on
 * purpose :-(.
 */


typedef struct msr_struct
{
	unsigned lo;
	unsigned hi;
} msr_t;

static inline msr_t rdmsr(unsigned index)
{
	msr_t result;
	result.lo = 0;
	result.hi = 0;
	return result;
}

static void sis761_read_resources(device_t dev)
{
	/* Read the generic PCI resources */
	printk_debug("sis761_read_resources ------->\n");
	pci_dev_read_resources(dev);

	/* If we are not the first processor don't allocate the gart apeture */
	if (dev->path.pci.devfn != PCI_DEVFN(0x0, 0)) {
		printk_debug("sis761_not_the_first_processor !!!\n");
		return;
	}

	printk_debug("sis761_read_resources <-------\n");
	return;

}

static void sis761_set_resources(device_t dev)
{
	printk_debug("sis761_set_resources ------->\n");

	/* Set the generic PCI resources */
	pci_dev_set_resources(dev);
	printk_debug("sis761_set_resources <-------\n");
}

static void sis761_init(struct device *dev)
{
	int needs_reset;
	msr_t	msr;


	needs_reset = 0;
	printk_debug("sis761_init: ---------->\n");

	msr = rdmsr(0xC001001A);
	pci_write_config16(dev, 0x8E, msr.lo >> 16);				// Topbound
	pci_write_config8(dev, 0x7F, 0x08);			// ACPI Base
	outb(inb(0x856) | 0x40, 0x856);	 // Auto-Reset Function

	printk_debug("sis761_init: <----------\n");
}


static struct device_operations sis761_ops  = {
	.read_resources   = sis761_read_resources,
	.set_resources    = sis761_set_resources,
	.enable_resources = pci_dev_enable_resources,
	.init             = sis761_init,
	.scan_bus         = 0,
	.ops_pci          = 0,
};

static const struct pci_driver sis761_driver __pci_driver = {
	.ops    = &sis761_ops,
	.vendor = PCI_VENDOR_ID_SIS,
	.device = PCI_DEVICE_ID_SIS_SIS761,
};