blob: a4e8fe07607609aaf9c066200b92d429a32696ea (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
|
##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config SOUTHBRIDGE_INTEL_SCH
bool
select SOUTHBRIDGE_INTEL_COMMON
select HAVE_USBDEBUG
select HAVE_HARD_RESET
select HAVE_SMI_HANDLER
if SOUTHBRIDGE_INTEL_SCH
config EHCI_BAR
hex
default 0xfef00000
config HAVE_CMC
bool "Add a CMC state machine binary"
help
Select this option to add a CMC state machine binary to
the resulting coreboot image.
Note: Without this binary coreboot will not work
config CMC_FILE
string "Intel CMC path and filename"
depends on HAVE_CMC
default "cmc.bin"
help
The path and filename of the file to use as CMC state machine
binary.
config HPET_MIN_TICKS
hex
default 0x80
endif
|
