blob: b423ecae40a8d1b8885a4d8eecb70c96cf71bfdd (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
|
##
## This file is part of the coreboot project.
##
## Copyright (C) 2008-2009 coresystems GmbH
## 2012 secunet security Networks AG
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config SOUTHBRIDGE_INTEL_I82801JX
bool
select SOUTHBRIDGE_INTEL_COMMON
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI
select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
select SOUTHBRIDGE_INTEL_COMMON_PMCLIB
select IOAPIC
select HAVE_USBDEBUG
select USE_WATCHDOG_ON_BOOT
select HAVE_SMI_HANDLER
select HAVE_USBDEBUG_OPTIONS
select SOUTHBRIDGE_INTEL_COMMON_GPIO
select INTEL_DESCRIPTOR_MODE_CAPABLE
select COMMON_FADT
select SOUTHBRIDGE_INTEL_COMMON_SMM
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select HAVE_POWER_STATE_AFTER_FAILURE
select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
if SOUTHBRIDGE_INTEL_I82801JX
config EHCI_BAR
hex
default 0xfef00000
## Some enterprise variants may require an IFD
config INTEL_DESCRIPTOR_MODE_REQUIRED
bool
default n
config HPET_MIN_TICKS
hex
default 0x80
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/intel/i82801jx/bootblock.c"
endif
|
