blob: f03e11c312f08b55126b7161f3ea2a67179509a8 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
|
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef SOUTHBRIDGE_INTEL_SPI_H
#define SOUTHBRIDGE_INTEL_SPI_H
enum optype {
READ_NO_ADDR = 0,
WRITE_NO_ADDR = 1,
READ_WITH_ADDR = 2,
WRITE_WITH_ADDR = 3
};
struct intel_spi_op {
u8 op;
enum optype type;
};
struct intel_swseq_spi_config {
u8 opprefixes[2];
struct intel_spi_op ops[8];
};
void spi_finalize_ops(void);
void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config);
#endif
|