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##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Advanced Micro Devices, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config SOUTHBRIDGE_AMD_SB700
bool
if SOUTHBRIDGE_AMD_SB700
config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
def_bool y
select IOAPIC
select HAVE_USBDEBUG_OPTIONS
select SMBUS_HAS_AUX_CHANNELS
config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI
bool "Enable high speed SPI clock"
default n
help
When set, the SPI clock will run at 33MHz instead
of the compatibility mode 16.5MHz. Note that not
all ROMs are capable of 33MHz operation, so you
will need to verify this option is appropriate for
the ROM you are using.
# Set for southbridge SP5100 which also uses SB700 driver
config SOUTHBRIDGE_AMD_SUBTYPE_SP5100
bool
default n
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/amd/sb700/bootblock.c"
config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
bool
default n
config SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA
bool
default n
config SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD
hex
default 0xf
config EHCI_BAR
hex
default 0xfef00000
config HPET_MIN_TICKS
hex
default 0x14
endif # SOUTHBRIDGE_AMD_SB700
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