Makefile.inc « riscv « ucb « soc « src - coreboot.git - my copy of coreboot

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path: root/src/soc/ucb/riscv/Makefile.inc

blob: 1072a2b32ec96feec4ee374bb8caca6f636b0330 (plain)

ifeq ($(CONFIG_SOC_UCB_RISCV),y)

romstage-y += cbmem.c
ramstage-y += cbmem.c

endif