1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
|
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/mmio.h>
#include <boot/coreboot_tables.h>
#include <console/uart.h>
#include <soc/clk.h>
#include <soc/cpu.h>
#include <soc/periph.h>
#include <soc/uart.h>
#include <types.h>
#define RX_FIFO_COUNT_MASK 0xff
#define RX_FIFO_FULL_MASK (1 << 8)
#define TX_FIFO_FULL_MASK (1 << 24)
static void serial_setbrg_dev(struct s5p_uart *uart)
{
u32 uclk;
u32 val;
// All UARTs share the same clock.
uclk = clock_get_periph_rate(PERIPH_ID_UART3);
val = uclk / get_uart_baudrate();
write32(&uart->ubrdiv, val / 16 - 1);
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*/
static void exynos5_init_dev(struct s5p_uart *uart)
{
/* enable FIFOs */
write32(&uart->ufcon, 0x1);
write32(&uart->umcon, 0);
/* 8N1 */
write32(&uart->ulcon, 0x3);
/* No interrupts, no DMA, pure polling */
write32(&uart->ucon, 0x245);
serial_setbrg_dev(uart);
}
static int exynos5_uart_err_check(struct s5p_uart *uart, int op)
{
unsigned int mask;
/*
* UERSTAT
* Break Detect [3]
* Frame Err [2] : receive operation
* Parity Err [1] : receive operation
* Overrun Err [0] : receive operation
*/
if (op)
mask = 0x8;
else
mask = 0xf;
return read32(&uart->uerstat) & mask;
}
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise. When the function is successful, the character read is
* written into its argument c.
*/
static unsigned char exynos5_uart_rx_byte(struct s5p_uart *uart)
{
/* wait for character to arrive */
while (!(read32(&uart->ufstat) & (RX_FIFO_COUNT_MASK |
RX_FIFO_FULL_MASK))) {
if (exynos5_uart_err_check(uart, 0))
return 0;
}
return read8(&uart->urxh) & 0xff;
}
/*
* Output a single byte to the serial port.
*/
static void exynos5_uart_tx_byte(struct s5p_uart *uart, unsigned char data)
{
/* wait for room in the tx FIFO */
while ((read32(&uart->ufstat) & TX_FIFO_FULL_MASK)) {
if (exynos5_uart_err_check(uart, 1))
return;
}
write8(&uart->utxh, data);
}
uintptr_t uart_platform_base(unsigned int idx)
{
if (idx < 4)
return 0x12c00000 + idx * 0x10000;
else
return 0;
}
void uart_init(unsigned int idx)
{
struct s5p_uart *uart = uart_platform_baseptr(idx);
exynos5_init_dev(uart);
}
unsigned char uart_rx_byte(unsigned int idx)
{
struct s5p_uart *uart = uart_platform_baseptr(idx);
return exynos5_uart_rx_byte(uart);
}
void uart_tx_byte(unsigned int idx, unsigned char data)
{
struct s5p_uart *uart = uart_platform_baseptr(idx);
exynos5_uart_tx_byte(uart, data);
}
void uart_tx_flush(unsigned int idx)
{
/* Exynos5250 implements this too. */
}
enum cb_err fill_lb_serial(struct lb_serial *serial)
{
serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial->baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
serial->baud = get_uart_baudrate();
serial->regwidth = 4;
serial->input_hertz = uart_platform_refclk();
return CB_SUCCESS;
}
|
