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config CPU_SAMSUNG_EXYNOS5420
select ARCH_BOOTBLOCK_ARMV7
select ARCH_ROMSTAGE_ARMV7
select ARCH_RAMSTAGE_ARMV7
select CPU_HAS_BOOTBLOCK_INIT
select HAVE_MONOTONIC_TIMER
select HAVE_UART_SPECIAL
select RELOCATABLE_MODULES
select DYNAMIC_CBMEM
bool
default n
if CPU_SAMSUNG_EXYNOS5420
# ROM image layout.
#
# 0x0000: vendor-provided BL1 (8k).
# 0x2000: variable length bootblock checksum header
# 0x2010: bootblock
# 0x9F80-0xA000: reserved for CBFS master header.
# 0xA000: Free for CBFS data.
config BOOTBLOCK_ROM_OFFSET
hex
default 0
config CBFS_HEADER_ROM_OFFSET
hex "offset of master CBFS header in ROM"
default 0x9F80
config CBFS_ROM_OFFSET
# Calculated by BOOTBLOCK_ROM_OFFSET + max bootblock size.
hex "offset of CBFS data in ROM"
default 0x0A000
config SYS_SDRAM_BASE
hex
default 0x20000000
# Example SRAM/iRAM map for Exynos5420 platform:
#
# 0x0202_0000: vendor-provided BL1
# 0x0202_4400: variable length bootblock checksum header.
# 0x0202_4410: bootblock, assume up to 32KB in size
# 0x0203_0000: romstage, assume up to 128KB in size.
# 0x0205_8000: TTB buffer.
# 0x0205_c000: cache for CBFS data.
# 0x0206_f000: stack bottom
# 0x0207_3000: stack pointer
# 0x0207_3000: shared (with kernel) page for cpu & secondary core states.
# the shared data is currently only <0x50 bytes so we can share
# this page with stack.
config BOOTBLOCK_BASE
hex
default 0x02024410
config ROMSTAGE_BASE
hex
default 0x02030000
config RAMSTAGE_BASE
hex
default SYS_SDRAM_BASE
# Stack may reside in either IRAM or DRAM. We will define it to live
# at the top of IRAM for now.
#
# Stack grows downward, push operation stores register contents in
# consecutive memory locations ending just below SP.
# The setup in the exynos 5420 is a new one for coreboot. We have got
# the bootblock, romstage, and ramstage sharing the same stack space.
# The SRAM is always there and having a known-good stack memory
# makes for a more reliable setup.
# Thus, in this case:
# STACK_TOP: highest stack address in SRAM
# STACK_BOTTOM: lowest stack address in SRAM
# STACK_SIZE: as in standard coreboot usage, size of thread stacks in ramstage
# ROMSTAGE_STACK_SIZE: size of the single stack in romstage
config STACK_TOP
hex
default 0x02073000
config STACK_BOTTOM
hex
default 0x0206f000
# STACK_SIZE is for the ramstage core and thread stacks.
# It must be a power of 2, to make the cpu_info computation work,
# and cpu_info needs to work to make SMP startup and threads work.
config STACK_SIZE
hex
default 0x0800
# TODO We may probably move this to board-specific implementation files instead
# of KConfig values.
config CBFS_CACHE_ADDRESS
hex "memory address to put CBFS cache data"
default 0x0205c000
config CBFS_CACHE_SIZE
hex "size of CBFS cache data"
default 0x00013000
config TTB_BUFFER
hex "memory address of the TTB buffer"
default 0x02058000
endif
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