blob: 7eb0ef054ddf4938e20f936f1c8b54d24dafd96e (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
|
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
#include <gpio.h>
#include <soc/gpio.h>
#include <soc/grf.h>
#include <soc/pmu.h>
#include <soc/soc.h>
struct rockchip_gpio_regs *gpio_port[] = {
(struct rockchip_gpio_regs *)0xff750000,
(struct rockchip_gpio_regs *)0xff780000,
(struct rockchip_gpio_regs *)0xff790000,
(struct rockchip_gpio_regs *)0xff7a0000,
(struct rockchip_gpio_regs *)0xff7b0000,
(struct rockchip_gpio_regs *)0xff7c0000,
(struct rockchip_gpio_regs *)0xff7d0000,
(struct rockchip_gpio_regs *)0xff7e0000,
(struct rockchip_gpio_regs *)0xff7f0000
};
#define PMU_GPIO_PORT 0
int is_pmu_gpio(gpio_t gpio)
{
if (gpio.port == PMU_GPIO_PORT)
return 1;
return 0;
}
void *gpio_grf_reg(gpio_t gpio)
{
if (is_pmu_gpio(gpio))
return &rk3288_pmu->gpio0pull[gpio.bank];
/* There is one pmu gpio, gpio0, so " - 1" */
return &rk3288_grf->gpio1_p[(gpio.port - 1)][gpio.bank];
}
u32 gpio_get_pull_val(gpio_t gpio, enum gpio_pull pull)
{
/* use the default gpio pull bias setting defined in soc/gpio.h */
return pull;
}
|