blob: 1b825151c6f8c8e222e0c4a420135f791d147573 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
|
##
## This file is part of the coreboot project.
##
## Copyright 2014 Rockchip Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc.
##
config SOC_ROCKCHIP_RK3288
bool
default n
select ARCH_BOOTBLOCK_ARMV7
select ARCH_VERSTAGE_ARMV7
select ARCH_ROMSTAGE_ARMV7
select ARCH_RAMSTAGE_ARMV7
select HAVE_MONOTONIC_TIMER
select GENERIC_UDELAY
select HAVE_UART_SPECIAL
select BOOTBLOCK_CONSOLE
select UNCOMPRESSED_RAMSTAGE
select GENERIC_GPIO_LIB
select RTC
if SOC_ROCKCHIP_RK3288
config BOOTBLOCK_CPU_INIT
string
default "soc/rockchip/rk3288/bootblock.c"
config PMIC_BUS
int
default -1
endif
|
