1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
|
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <memlayout.h>
#include <arch/header.ld>
/*
* Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself,
* so the bootblock loading address must be placed after that. After the
* handoff that area may be reclaimed for other uses, e.g. CBFS cache.
* TODO: Did this change on Tegra132? What's the new valid range?
*/
SECTIONS
{
SRAM_START(0x40000000)
/* 16K hole */
PRERAM_CBMEM_CONSOLE(0x40004000, 8K)
CBFS_CACHE(0x40006000, 88K)
STACK(0x4001C000, 16K)
BOOTBLOCK(0x40020000, 20K)
ROMSTAGE(0x40025000, 108K)
SRAM_END(0x40040000)
DRAM_START(0x80000000)
RAMSTAGE(0x80200000, 192K)
}
|
