1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
|
/*
* This file is part of the coreboot project.
*
* Copyright (c) 2014, NVIDIA CORPORATION.
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <soc/addressmap.h>
#include <soc/clock.h>
#include <soc/padconfig.h>
#include <soc/nvidia/tegra/i2c.h>
#include <soc/nvidia/tegra132/power.h>
#include <soc/nvidia/tegra132/clk_rst.h>
#include "delay.h"
#define I2C6_BUS 5
#define I2C6_PADCTL 0xC001
#define DPAUX_HYBRID_PADCTL 0x545C0124
static struct tegra_pmc_regs * const pmc = (void *)TEGRA_PMC_BASE;
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
static int partition_clamp_on(int id)
{
return read32(&pmc->clamp_status) & (1 << id);
}
static void remove_clamps(int id)
{
if (!partition_clamp_on(id))
return;
/* Remove clamp */
write32((1 << id), &pmc->remove_clamping_cmd);
/* Wait for clamp off */
while (partition_clamp_on(id))
;
}
static void enable_sor_periph_clocks(void)
{
setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_HOST1X);
setbits_le32(&clk_rst->clk_out_enb_x, CLK_X_DPAUX);
/* Give clocks time to stabilize. */
udelay(IO_STABILIZATION_DELAY);
}
static void disable_sor_periph_clocks(void)
{
clrbits_le32(&clk_rst->clk_out_enb_l, CLK_L_HOST1X);
clrbits_le32(&clk_rst->clk_out_enb_x, CLK_X_DPAUX);
/* Give clocks time to stabilize. */
udelay(IO_STABILIZATION_DELAY);
}
static void unreset_sor_periphs(void)
{
clrbits_le32(&clk_rst->rst_dev_l, CLK_L_HOST1X);
clrbits_le32(&clk_rst->rst_dev_x, CLK_X_DPAUX);
}
void soc_configure_i2c6pad(void)
{
/*
* I2C6 on Tegra124/132 requires some special init.
* The SOR block must be unpowergated, and a couple of
* display-based peripherals must be clocked and taken
* out of reset so that a DPAUX register can be
* configured to enable the I2C6 mux routing.
* Afterwards, we can disable clocks to the display blocks
* and put Host1X back in reset. DPAUX must remain out of
* reset and the SOR partition must remained unpowergated.
*/
power_ungate_partition(POWER_PARTID_SOR);
/* Host1X needs a valid clock source so DPAUX can be accessed */
clock_configure_source(host1x, PLLP, 204000);
enable_sor_periph_clocks();
remove_clamps(POWER_PARTID_SOR);
unreset_sor_periphs();
/* Now we can write the I2C6 mux in DPAUX */
write32(I2C6_PADCTL, (void *)DPAUX_HYBRID_PADCTL);
/*
* Delay before turning off Host1X/DPAUX clocks.
* This delay is needed to keep the sequence from
* hanging the system.
*/
udelay(CLOCK_PLL_STABLE_DELAY_US);
/* Stop Host1X/DPAUX clocks and reset Host1X */
disable_sor_periph_clocks();
setbits_le32(&clk_rst->rst_dev_l, CLK_L_HOST1X);
}
|
