blob: 7862dd5b7be95d4d2bcb58dac94b6571aa9ae3e6 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
|
config SOC_NVIDIA_TEGRA124
select ARCH_BOOTBLOCK_ARMV4
select ARCH_ROMSTAGE_ARMV7
select ARCH_RAMSTAGE_ARMV7
select HAVE_UART_SPECIAL
select BOOTBLOCK_CONSOLE
select DYNAMIC_CBMEM
select ARM_BOOTBLOCK_CUSTOM
bool
default n
if SOC_NVIDIA_TEGRA124
config BOOTBLOCK_CPU_INIT
string
default "soc/nvidia/tegra124/bootblock.c"
help
CPU/SoC-specific bootblock code. This is useful if the
bootblock must load microcode or copy data from ROM before
searching for the bootblock.
# ROM image layout.
#
# 0x00000 Combined bootblock and BCT blob
# 0x18000 Master CBFS header.
# 0x18080 Free for CBFS data.
#
# iRAM (256k) layout.
# (Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself,
# so the bootblock loading address must be placed after that. After the
# handoff that area may be reclaimed for other uses, e.g. CBFS cache.)
#
# 0x4000_0000 TTB (16K+32B). 32B is for L1 table of LPAE.
# 0x4000_4020 CBMEM console area (8K-32B)
# 0x4000_6000 CBFS mapping cache (88K)
# 0x4001_C000 Stack (16KB... don't reduce without comparing LZMA scratchpad!).
# 0x4002_0000 Bootblock (max 48KB).
# 0x4002_C000 ROM stage (max 80KB).
# 0x4003_FFFF End of iRAM.
config BOOTBLOCK_ROM_OFFSET
hex
default 0x0
config CBFS_HEADER_ROM_OFFSET
hex "offset of master CBFS header in ROM"
default 0x18000
config CBFS_ROM_OFFSET
hex "offset of CBFS data in ROM"
default 0x18080
config SYS_SDRAM_BASE
hex
default 0x80000000
config BOOTBLOCK_BASE
hex
default 0x40020000
config ROMSTAGE_BASE
hex
default 0x4002c000
config RAMSTAGE_BASE
hex
default 0x80200000
config STACK_TOP
hex
default 0x40020000
config STACK_BOTTOM
hex
default 0x4001c000
# This is the ramstage thread stack, *not* the same as above! Currently unused.
config STACK_SIZE
hex
default 0x800
# TTB needs to be aligned to 16KB. Stick it in iRAM.
config TTB_BUFFER
hex "memory address of the TTB buffer"
default 0x40000000
config CBFS_CACHE_ADDRESS
hex "memory address to put CBFS cache data"
default 0x40006000
config CBFS_CACHE_SIZE
hex "size of CBFS cache data"
default 0x00016000
config CBMEM_CONSOLE_PRERAM_BASE
hex "memory address of the CBMEM console buffer"
default 0x40004020
config TEGRA124_MODEL_TD570D
bool "TD570D"
config TEGRA124_MODEL_TD580D
bool "TD580D"
config TEGRA124_MODEL_CD570M
bool "CD570M"
config TEGRA124_MODEL_CD580M
bool "CD580M"
# Default to 2GHz, the lowest maximum frequency.
config PLLX_KHZ
int
default 2000000 if TEGRA124_MODEL_TD570D
default 2300000 if TEGRA124_MODEL_TD580D
default 2100000 if TEGRA124_MODEL_CD570M
default 2300000 if TEGRA124_MODEL_CD580M
default 2000000
endif
|
