1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
|
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/mmio.h>
#include <gpio.h>
static void *gpio_find_reg_addr(gpio_t gpio)
{
void *reg_addr;
switch (gpio.base & 0x0f) {
case 0:
reg_addr = (void *)IOCFG_BL_BASE;
break;
case 1:
reg_addr = (void *)IOCFG_BM_BASE;
break;
case 2:
reg_addr = (void *)IOCFG_BR_BASE;
break;
case 3:
reg_addr = (void *)IOCFG_LM_BASE;
break;
case 4:
reg_addr = (void *)IOCFG_RB_BASE;
break;
case 5:
reg_addr = (void *)IOCFG_TL_BASE;
break;
default:
reg_addr = NULL;
break;
}
return reg_addr;
}
static void gpio_set_spec_pull_pupd(gpio_t gpio, enum pull_enable enable,
enum pull_select select)
{
void *reg1;
void *reg2;
int bit = gpio.bit;
reg1 = gpio_find_reg_addr(gpio) + gpio.offset;
reg2 = reg1 + (gpio.base & 0xf0);
if (enable == GPIO_PULL_ENABLE) {
if (select == GPIO_PULL_DOWN)
setbits32(reg1, 1 << bit);
else
clrbits32(reg1, 1 << bit);
}
if (enable == GPIO_PULL_ENABLE) {
setbits32(reg2, 1 << bit);
} else {
clrbits32(reg2, 1 << bit);
clrbits32(reg2 + 0x010, 1 << bit);
}
}
static void gpio_set_pull_pu_pd(gpio_t gpio, enum pull_enable enable,
enum pull_select select)
{
void *reg1;
void *reg2;
int bit = gpio.bit;
reg1 = gpio_find_reg_addr(gpio) + gpio.offset;
reg2 = reg1 - (gpio.base & 0xf0);
if (enable == GPIO_PULL_ENABLE) {
if (select == GPIO_PULL_DOWN) {
clrbits32(reg1, 1 << bit);
setbits32(reg2, 1 << bit);
} else {
clrbits32(reg2, 1 << bit);
setbits32(reg1, 1 << bit);
}
} else {
clrbits32(reg1, 1 << bit);
clrbits32(reg2, 1 << bit);
}
}
void gpio_set_pull(gpio_t gpio, enum pull_enable enable,
enum pull_select select)
{
if (gpio.flag)
gpio_set_spec_pull_pupd(gpio, enable, select);
else
gpio_set_pull_pu_pd(gpio, enable, select);
}
|
