src/soc/intel/xeon_sp/cpx/ramstage.c


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/* SPDX-License-Identifier: GPL-2.0-only */

#include <fsp/api.h>
#include <smbios.h>

int soc_fsp_multi_phase_init_is_enable(void)
{
	return 0;
}

unsigned int smbios_cpu_get_max_speed_mhz(void)
{
	return 3900;
}