blob: f8ef01a6df3742543f7632c339034a33c862c207 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <arch/io.h>
#include <cbmem.h>
#include <device/pci.h>
#include <soc/pci_devs.h>
#include <soc/romstage.h>
#include <soc/smm.h>
#include <soc/systemagent.h>
size_t mmap_region_granluarity(void)
{
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER))
/* Align to TSEG size when SMM is in use */
if (CONFIG_SMM_TSEG_SIZE != 0)
return CONFIG_SMM_TSEG_SIZE;
/* Make it 8MiB by default. */
return 8 << 20;
}
static void *smm_region_start(void)
{
/*
* SMM base address matches the top of DPR. The DPR register has
* 1 MiB alignment and reports the TOP of the DPR range.
*/
uint32_t smm_base = pci_read_config32(SA_DEV_ROOT, DPR);
smm_base = ALIGN_DOWN(smm_base, 1 << 20);
return (void *)smm_base;
}
void smm_region(void **start, size_t *size)
{
*start = smm_region_start();
*size = mmap_region_granluarity();
}
void *cbmem_top(void)
{
/*
* +-------------------------+ Top of RAM (aligned)
* | System Management Mode |
* | code and data | Length: CONFIG_TSEG_SIZE
* | (TSEG) |
* +-------------------------+ SMM base (aligned)
* | |
* | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE
* | |
* +-------------------------+ top_of_ram (aligned)
* | |
* | CBMEM Root |
* | |
* +-------------------------+
* | |
* | FSP Reserved Memory |
* | |
* +-------------------------+
* | |
* | Various CBMEM Entries |
* | |
* +-------------------------+ top_of_stack (8 byte aligned)
* | |
* | stack (CBMEM Entry) |
* | |
* +-------------------------+
*/
unsigned long top_of_ram = (unsigned long)smm_region_start();
/*
* Subtract DMA Protected Range size if enabled and align to a multiple
* of TSEG size.
*/
u32 dpr = pci_read_config32(SA_DEV_ROOT, DPR);
if (dpr & DPR_EPM) {
top_of_ram -= (dpr & DPR_SIZE_MASK) << 16;
top_of_ram = ALIGN_DOWN(top_of_ram, mmap_region_granluarity());
}
return (void *)(top_of_ram - CONFIG_CHIPSET_RESERVED_MEM_BYTES);
}
|
