blob: f2a9e8b19fc16eb8d549938e7338e8726438d09b (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <bootstate.h>
#include <chip.h>
#include <soc/lpc.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <string.h>
static void lpc_lockdown_config(void)
{
static struct soc_intel_skylake_config *config;
struct device *dev;
uint8_t reg_mask = 0;
dev = PCH_DEV_LPC;
/* Check if LPC is enabled, else return */
if (dev == NULL || dev->chip_info == NULL)
return;
config = dev->chip_info;
/* Set Bios Interface Lock, Bios Lock */
if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT)
reg_mask |= LPC_BC_BILD | LPC_BC_LE;
pci_or_config8(dev, BIOS_CNTL, reg_mask);
/* Ensure an additional read back after performing lock down */
pci_read_config8(dev, BIOS_CNTL);
}
static void pmc_lockdown_config(void)
{
uint8_t *pmcbase;
u32 pmsyncreg;
/* PMSYNC */
pmcbase = pmc_mmio_regs();
pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
pmsyncreg |= PMSYNC_LOCK;
write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
}
static void platform_lockdown_config(void *unused)
{
/* LPC lock down configuration */
lpc_lockdown_config();
/* PMC lock down configuration */
pmc_lockdown_config();
}
BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config,
NULL);
|
