1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
Device (PMC)
{
Name (_ADR, 0x001f0002)
Name (_DDN, "Power Management Controller")
OperationRegion (PMCP, PCI_Config, 0x00, 0x100)
Field (PMCP, AnyAcc, NoLock, Preserve)
{
Offset (0x48),
, 12,
PWRM, 20, /* PWRMBASE */
}
OperationRegion (PMCM, SystemMemory, ShiftLeft (PWRM, 12), 0x3f)
Field (PMCM, DWordAcc, NoLock, Preserve)
{
Offset (0x1c), /* PCH_PM_STS */
, 24,
PMFS, 1, /* PMC_MSG_FULL_STS */
Offset (0x20),
MPMC, 32, /* MTPMC */
Offset (0x24), /* PCH_PM_STS2 */
, 20,
UWAB, 1, /* USB2 Workaround Available */
}
}
|
