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##
## This file is part of the coreboot project.
##
## Copyright (C) 2015-2016 Intel Corp.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config SOC_INTEL_QUARK
bool
help
Intel Quark support
if SOC_INTEL_QUARK
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_BOOTBLOCK_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
select BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP
select C_ENVIRONMENT_BOOTBLOCK
select HAVE_HARD_RESET
select REG_SCRIPT
select RELOCATABLE_RAMSTAGE
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_RESET
select SOC_SETS_MSRS
select TSC_CONSTANT_RATE
select UART_OVERRIDE_REFCLK
select UDELAY_TSC
select UNCOMPRESSED_RAMSTAGE
select USE_MARCH_586
#####
# Debug serial output
# The following options configure the debug serial port
#####
config ENABLE_BUILTIN_HSUART0
bool "Enable built-in HSUART0"
default n
select NO_UART_ON_SUPERIO
select DRIVERS_UART_8250MEM_32
help
The Quark SoC has two HSUART. Choose this option to configure the pads
and enable HSUART0, which can be used for the debug console.
config ENABLE_BUILTIN_HSUART1
bool "Enable built-in HSUART1"
default n
depends on ! ENABLE_BUILTIN_HSUART0
select NO_UART_ON_SUPERIO
select DRIVERS_UART_8250MEM_32
help
The Quark SoC has two HSUART. Choose this option to configure the pads
and enable HSUART1, which can be used for the debug console.
config TTYS0_BASE
hex "HSUART Base Address"
default 0xA0019000
depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1
help
Memory mapped MMIO of HSUART.
config TTYS0_LCS
int
default 3
depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1
# Console: PCI UART bus 0 << 20, device 20 << 15, function x << 12
# Valid bit, PCI UART in use: 1 << 31
config UART_PCI_ADDR
hex
default 0x800a1000 if ENABLE_BUILTIN_HSUART0
default 0x800a5000 if ENABLE_BUILTIN_HSUART1
depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1
#####
# Debug support
# The following options provide debug support for the Quark coreboot
# code. The SD LED is used as a binary marker to determine if a
# specific point in the execution flow has been reached.
#####
config ENABLE_DEBUG_LED
bool
default n
help
Enable the use of the SD LED for early debugging before serial output
is available. Setting this LED indicates that control has reached the
desired check point.
config ENABLE_DEBUG_LED_ESRAM
bool "SD LED indicates ESRAM initialized"
default n
select ENABLE_DEBUG_LED
help
Indicate that ESRAM has been successfully initialized.
config ENABLE_DEBUG_LED_FINDFSP
bool "SD LED indicates fsp.bin file was found"
default n
select ENABLE_DEBUG_LED
help
Indicate that fsp.bin was found.
config ENABLE_DEBUG_LED_TEMPRAMINIT
bool "SD LED indicates TempRamInit was successful"
default n
select ENABLE_DEBUG_LED
help
Indicate that TempRamInit was successful.
#####
# ESRAM layout
# Specify the portion of the ESRAM for coreboot to use as its data area.
#####
config DCACHE_RAM_BASE
hex
default 0x80070000
config DCACHE_RAM_SIZE
hex
default 0x00008000
#####
# Flash layout
# Specify the size of the coreboot file system in the read-only
# (recovery) portion of the flash part.
#####
config CBFS_SIZE
hex
default 0x200000
help
Specify the size of the coreboot file system in the read-only (recovery)
portion of the flash part. On Quark systems the firmware image stores
more than just coreboot, including:
- The chipset microcode (RMU) binary file located at 0xFFF00000
- Intel Trusted Execution Engine firmware
#####
# FSP binary
# The following options control the FSP binary file placement in
# the flash image and ESRAM. This file is required by the Quark
# SoC code to boot coreboot and its payload.
#####
config ADD_FSP_RAW_BIN
bool "Add the Intel FSP binary to the flash image without relocation"
default n
depends on PLATFORM_USES_FSP1_1
help
Select this option to add an Intel FSP binary to
the resulting coreboot image.
Note: Without this binary, coreboot builds relying on the FSP
will not boot
config FSP_FILE
string "Intel FSP binary path and filename"
default "3rdparty/blobs/soc/intel/quark/fsp.bin"
depends on PLATFORM_USES_FSP1_1
depends on ADD_FSP_RAW_BIN
help
The path and filename of the Intel FSP binary for this platform.
config FSP_IMAGE_ID_STRING
string "8 byte platform string identifying the FSP platform"
default "QUK-FSP0"
depends on PLATFORM_USES_FSP1_1
help
8 ASCII character byte signature string that will help match the FSP
binary to a supported hardware configuration.
config FSP_LOC
hex
default 0xfff80000
depends on PLATFORM_USES_FSP1_1
help
The location in CBFS that the FSP is located. This must match the
value that is set in the FSP binary. If the FSP needs to be moved,
rebase the FSP with Intel's BCT (tool).
config FSP_ESRAM_LOC
hex
default 0x80000000
depends on PLATFORM_USES_FSP1_1
help
The location in ESRAM where a copy of the FSP binary is placed.
config RELOCATE_FSP_INTO_DRAM
bool "Relocate FSP into DRAM"
default n
depends on PLATFORM_USES_FSP1_1
help
Relocate the FSP binary into DRAM before the call to SiliconInit.
#####
# RMU binary
# The following options control the Quark chipset microcode file
# placement in the flash image. This file is required to bring
# the Quark processor out of reset.
#####
config ADD_RMU_FILE
bool "Should the RMU binary be added to the flash image?"
default n
help
The RMU file is required to get the chip out of reset.
config RMU_FILE
string
default "3rdparty/blobs/soc/intel/quark/rmu.bin"
depends on ADD_RMU_FILE
help
The path and filename of the Intel Quark RMU binary.
config RMU_LOC
hex
default 0xfff00000
depends on ADD_RMU_FILE
help
The location in CBFS that the RMU is located. It must match the
strap-determined base address.
#####
# Bootblock
# The following options support the C_ENVIRONMENT_BOOTBLOCK.
#####
config DCACHE_BSP_STACK_SIZE
hex
default 0x4000
config C_ENV_BOOTBLOCK_SIZE
hex
default 0x8000
endif # SOC_INTEL_QUARK
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