1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/acpi.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <intelblocks/lpss.h>
#include <intelblocks/uart.h>
#define UART_PCI_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)
static void uart_lpss_init(uintptr_t baseaddr)
{
/* Take UART out of reset */
lpss_reset_release(baseaddr);
/* Set M and N divisor inputs and enable clock */
lpss_clk_update(baseaddr, CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL,
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL);
}
void uart_common_init(device_t dev, uintptr_t baseaddr)
{
/* Set UART base address */
pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr);
/* Enable memory access and bus master */
pci_write_config32(dev, PCI_COMMAND, UART_PCI_ENABLE);
uart_lpss_init(baseaddr);
}
__attribute__((weak)) device_t pch_uart_get_debug_controller(void)
{
/*
* device_t can either be a pointer to struct device (e.g. ramstage) or
* a simple integer (e.g. SMM) depending upon whether __SIMPLE_DEVICE__
* is defined for the stage. Thus, the return requires additional
* casting to uintptr_t.
*/
return (device_t)(uintptr_t)NULL;
}
bool uart_debug_controller_is_initialized(void)
{
device_t dev;
uintptr_t base;
dev = pch_uart_get_debug_controller();
if (!dev)
return false;
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xFFF;
if (!base)
return false;
if ((pci_read_config32(dev, PCI_COMMAND) & UART_PCI_ENABLE)
!= UART_PCI_ENABLE)
return false;
return !lpss_is_controller_in_reset(base);
}
#if ENV_RAMSTAGE
__attribute__((weak)) void pch_uart_read_resources(struct device *dev)
{
pci_dev_read_resources(dev);
}
__attribute__((weak)) bool pch_uart_init_debug_controller_on_resume(void)
{
/* By default, do not initialize controller. */
return false;
}
bool uart_is_debug_controller(struct device *dev)
{
return dev == pch_uart_get_debug_controller();
}
/*
* This is a workaround to enable UART controller for the debug port if:
* 1. CONSOLE_SERIAL is not enabled in coreboot, and
* 2. This boot is S3 resume, and
* 3. SoC wants to initialize debug UART controller.
*
* This workaround is required because Linux kernel hangs on resume if console
* is not enabled in coreboot, but it is enabled in kernel and not suspended.
*/
static bool uart_controller_needs_init(struct device *dev)
{
/*
* If coreboot has CONSOLE_SERIAL enabled, the skip re-initializing
* controller here.
*/
if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))
return false;
/* If this device does not correspond to debug port, then skip. */
if (!uart_is_debug_controller(dev))
return false;
/* Initialize UART controller only on S3 resume. */
if (!acpi_is_wakeup_s3())
return false;
/*
* Call SoC specific routine to confirm it wants to initialize
* controller.
*/
return pch_uart_init_debug_controller_on_resume();
}
static void uart_common_enable_resources(struct device *dev)
{
pci_dev_enable_resources(dev);
if (uart_controller_needs_init(dev)) {
uintptr_t base;
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xFFF;
if (base)
uart_lpss_init(base);
}
}
static struct device_operations device_ops = {
.read_resources = &pch_uart_read_resources,
.set_resources = &pci_dev_set_resources,
.enable_resources = &uart_common_enable_resources,
.ops_pci = &pci_dev_ops_pci,
};
static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_INTEL_SPT_UART0,
PCI_DEVICE_ID_INTEL_SPT_UART1,
PCI_DEVICE_ID_INTEL_SPT_UART2,
PCI_DEVICE_ID_INTEL_SPT_H_UART0,
PCI_DEVICE_ID_INTEL_SPT_H_UART1,
PCI_DEVICE_ID_INTEL_SPT_H_UART2,
PCI_DEVICE_ID_INTEL_KBP_H_UART0,
PCI_DEVICE_ID_INTEL_KBP_H_UART1,
PCI_DEVICE_ID_INTEL_KBP_H_UART2,
PCI_DEVICE_ID_INTEL_APL_UART0,
PCI_DEVICE_ID_INTEL_APL_UART1,
PCI_DEVICE_ID_INTEL_APL_UART2,
PCI_DEVICE_ID_INTEL_APL_UART3,
PCI_DEVICE_ID_INTEL_CNL_UART0,
PCI_DEVICE_ID_INTEL_CNL_UART1,
PCI_DEVICE_ID_INTEL_CNL_UART2,
PCI_DEVICE_ID_INTEL_GLK_UART0,
PCI_DEVICE_ID_INTEL_GLK_UART1,
PCI_DEVICE_ID_INTEL_GLK_UART2,
PCI_DEVICE_ID_INTEL_GLK_UART3,
0,
};
static const struct pci_driver pch_uart __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
};
#endif /* ENV_RAMSTAGE */
|
