1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SOC_INTEL_COMMON_CSE_H
#define SOC_INTEL_COMMON_CSE_H
#include <stdint.h>
/* HFSTS register offsets in PCI config space */
enum {
PCI_ME_HFSTS1 = 0x40,
PCI_ME_HFSTS2 = 0x48,
PCI_ME_HFSTS3 = 0x60,
PCI_ME_HFSTS4 = 0x64,
PCI_ME_HFSTS5 = 0x68,
PCI_ME_HFSTS6 = 0x6C,
};
/* ME Host Firmware Status register 1 */
union me_hfsts1 {
u32 data;
struct {
u32 working_state: 4;
u32 mfg_mode: 1;
u32 fpt_bad: 1;
u32 operation_state: 3;
u32 fw_init_complete: 1;
u32 ft_bup_ld_flr: 1;
u32 update_in_progress: 1;
u32 error_code: 4;
u32 operation_mode: 4;
u32 reset_count: 4;
u32 boot_options_present: 1;
u32 reserved1: 1;
u32 bist_test_state: 1;
u32 bist_reset_request: 1;
u32 current_power_source: 2;
u32 d3_support_valid: 1;
u32 d0i3_support_valid: 1;
} __packed fields;
};
/* set up device for use in early boot enviroument with temp bar */
void heci_init(uintptr_t bar);
/*
* Receive message into buff not exceeding maxlen. Message is considered
* successfully received if a 'complete' indication is read from ME side
* and there was enough space in the buffer to fit that message. maxlen
* is updated with size of message that was received. Returns 0 on failure
* and 1 on success.
* In case of error heci_reset() may be requiered.
*/
int heci_receive(void *buff, size_t *maxlen);
/*
* Send message msg of size len to host from host_addr to cse_addr.
* Returns 1 on success and 0 otherwise.
* In case of error heci_reset() may be requiered.
*/
int
heci_send(const void *msg, size_t len, uint8_t host_addr, uint8_t cse_addr);
/*
* Sends snd_msg of size snd_sz, and reads message into buffer pointed by
* rcv_msg of size rcv_sz
* Returns 0 on failure a 1 on success.
*/
int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t *rcv_sz);
/*
* Attempt device reset. This is useful and perhaps only thing left to do when
* CPU and CSE are out of sync or CSE fails to respond.
* Returns 0 on failure a 1 on success.
*/
int heci_reset(void);
/* Reads config value from a specified offset in the CSE PCI Config space. */
uint32_t me_read_config32(int offset);
/*
* Check if the CSE device is enabled in device tree. Also check if the device
* is visible on the PCI bus by reading config space.
* Return true if device present and config space enabled, else return false.
*/
bool is_cse_enabled(void);
/* Makes the host ready to communicate with CSE*/
void set_host_ready(void);
/*
* Polls for ME state 'HECI_OP_MODE_SEC_OVERRIDE' for 15 seconds.
* Returns 0 on failure a 1 on success.
*/
uint8_t wait_cse_sec_override_mode(void);
/*
* Sends GLOBAL_RESET_REQ cmd to CSE.The reset type can be
* GLOBAL_RESET/HOST_RESET_ONLY/CSE_RESET_ONLY.
* Returns -1 on failure a 0 on success.
*/
int send_heci_reset_req_message(uint8_t rst_type);
/*
* Send HMRFPO_ENABLE command.
* returns 0 on failure and 1 on success.
*/
int send_hmrfpo_enable_msg(void);
/*
* Send HMRFPO_GET_STATUS command.
* returns -1 on failure and 0 (DISABLED)/ 1 (LOCKED)/ 2 (ENABLED)
* on success.
*/
int send_hmrfpo_get_status_msg(void);
#define BIOS_HOST_ADDR 0x00
#define HECI_MKHI_ADDR 0x07
/* Command GLOBAL_RESET_REQ Reset Types */
#define GLOBAL_RESET 1
#define HOST_RESET_ONLY 2
#define CSE_RESET_ONLY 3
/*HMRFPO Status types */
#define MKHI_HMRFPO_DISABLED 0
#define MKHI_HMRFPO_LOCKED 1
#define MKHI_HMRFPO_ENABLED 2
#endif // SOC_INTEL_COMMON_MSR_H
|
