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config SOC_INTEL_COMMON
bool
help
common code for Intel SOCs
if SOC_INTEL_COMMON
config CACHE_MRC_SETTINGS
bool "Save cached MRC settings"
default n
if CACHE_MRC_SETTINGS
config MRC_SETTINGS_CACHE_BASE
hex
default 0xfffe0000
config MRC_SETTINGS_CACHE_SIZE
hex
default 0x10000
config MRC_SETTINGS_PROTECT
bool "Enable protection on MRC settings"
default n
endif # CACHE_MRC_SETTINGS
config DISPLAY_MTRRS
bool "MTRRs: Display the MTRR settings"
default n
config DISPLAY_SMM_MEMORY_MAP
bool "SMM: Display the SMM memory map"
default n
config SOC_INTEL_COMMON_RESET
bool
default n
config SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
bool
default n
config SOC_INTEL_COMMON_LPSS_I2C
bool
default n
help
This driver supports the Intel Low Power Subsystem (LPSS) I2C
controllers that are based on Synopsys DesignWare IP.
config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ
int
depends on SOC_INTEL_COMMON_LPSS_I2C
help
The clock speed that the I2C controller is running at, in MHz.
No default is set here as this is an SOC-specific value and must
be provided by the SOC when it selects this driver.
config SOC_SETS_MTRRS
bool
default n
help
The SoC needs uses different access methods for reading and writing
the MTRRs. Use SoC specific routines to handle the MTRR access.
config MMA
bool "enable MMA (Memory Margin Analysis) support"
default n
help
Set this option to y to enable MMA (Memory Margin Analysis) support
config MMA_BLOBS_PATH
string "Path to MMA blobs"
depends on MMA
default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/mma"
config ADD_VBT_DATA_FILE
bool "Add a Video Bios Table (VBT) binary to CBFS"
help
Add a VBT file data file to CBFS. The VBT describes the integrated
GPU and connections, and is needed by FSP in order to initialize the
display.
config VBT_FILE
string "VBT binary path and filename"
depends on ADD_VBT_DATA_FILE
help
The path and filename of the VBT binary.
config SOC_INTEL_COMMON_GFX_OPREGION
bool
default n
config SOC_INTEL_COMMON_SMI
bool
default n
config SOC_INTEL_COMMON_ACPI
bool
default n
config SOC_INTEL_COMMON_NHLT
bool
default n
endif # SOC_INTEL_COMMON
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