blob: 9f1cf3486229aa322f2350ec0bd37c27074a9848 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com>
* Copyright (C) 2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SOC_CANNONLAKE_SMBUS_H_
#define _SOC_CANNONLAKE_SMBUS_H_
/* PCI registers */
#define TCOBASE 0x50 /* TCO base address. */
#define TCOCTL 0x54
#define TCO_BASE_EN (1 << 8) /* TCO base enable. */
/* IO and MMIO registers under primary BAR */
/* Set address for PCH as SMBus slave role */
#define SMB_RCV_SLVA 0x09
/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */
#define TCO1_STS 0x04
#define TCO_TIMEOUT (1 << 3)
#define TCO2_STS 0x06
#define TCO2_STS_SECOND_TO (1 << 1)
#define TCO1_CNT 0x08
#define TCO_LOCK (1 << 12)
#define TCO_TMR_HLT (1 << 11)
/*
* Default slave address value for PCH. This value is set to match default
* value set by hardware. It is useful since PCH is able to respond even
* before CPU is up. This is reset by RSMRST# but not by PLTRST#.
*/
#define SMBUS_SLAVE_ADDR 0x44
#endif
|
