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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016-2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <chip.h>
#include <console/console.h>
#include <device/pci.h>
#include <fsp/api.h>
#include <fsp/api.h>
#include <fsp/util.h>
#include <romstage_handoff.h>
#include <soc/ramstage.h>
#include <string.h>
void soc_init_pre_device(void *chip_info)
{
/* Perform silicon specific init. */
fsp_silicon_init(romstage_handoff_is_resume());
}
struct chip_operations soc_intel_cannonlake_ops = {
CHIP_NAME("Intel Cannonlake")
.init = &soc_init_pre_device,
};
/* UPD parameters to be initialized before SiliconInit */
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
int i;
FSP_S_CONFIG *params = &supd->FspsConfig;
/* Set USB OC pin to 0 first */
for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) {
params->Usb2OverCurrentPin[i] = 0;
}
for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) {
params->Usb3OverCurrentPin[i] = 0;
}
mainboard_silicon_init_params(params);
}
/* Mainboard GPIO Configuration */
__attribute__((weak)) void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}
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