blob: f75a669266bfcec85d92031d4687ef0f5e79ecee (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
|
ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y)
subdirs-y += romstage
subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo
subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/x86/mtrr
subdirs-y += ../../../cpu/x86/tsc
bootblock-y += bootblock/bootblock.c
bootblock-y += bootblock/cpu.c
bootblock-y += bootblock/pch.c
bootblock-y += pmutil.c
bootblock-y += bootblock/report_platform.c
bootblock-y += gpio.c
bootblock-y += gspi.c
bootblock-y += memmap.c
bootblock-y += spi.c
bootblock-$(CONFIG_UART_DEBUG) += uart.c
romstage-y += gpio.c
romstage-y += gspi.c
romstage-y += memmap.c
romstage-y += pmutil.c
romstage-y += reset.c
romstage-y += spi.c
romstage-$(CONFIG_UART_DEBUG) += uart.c
ramstage-y += chip.c
ramstage-y += cpu.c
ramstage-y += gpio.c
ramstage-y += gspi.c
ramstage-y += memmap.c
ramstage-y += pmutil.c
ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
ramstage-y += spi.c
ramstage-y += systemagent.c
ramstage-$(CONFIG_UART_DEBUG) += uart.c
ramstage-y += vr_config.c
postcar-y += memmap.c
postcar-y += pmutil.c
postcar-y += spi.c
postcar-$(CONFIG_UART_DEBUG) += uart.c
verstage-y += gspi.c
verstage-y += pmutil.c
verstage-y += spi.c
verstage-$(CONFIG_UART_DEBUG) += uart.c
CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20
CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cannonlake
CPPFLAGS_common += -I$(src)/soc/intel/cannonlake
CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include
endif
|