blob: b95c8430c023b5a61d92547127c67303ef7a0145 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
|
config SOC_INTEL_CANNONLAKE
bool
help
Intel Cannonlake support
if SOC_INTEL_CANNONLAKE
config CPU_SPECIFIC_OPTIONS
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ARCH_BOOTBLOCK_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES
select C_ENVIRONMENT_BOOTBLOCK
select CACHE_MRC_SETTINGS
select COMMON_FADT
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select GENERIC_GPIO_LIB
select HAVE_FSP_GOP
select HAVE_HARD_RESET
select HAVE_INTEL_FIRMWARE
select HAVE_MONOTONIC_TIMER
select HAVE_SMI_HANDLER
select INTEL_CAR_NEM_ENHANCED
select INTEL_GMA_ACPI
select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP
select IOAPIC
select MRC_SETTINGS_PROTECT
select PARALLEL_MP
select PARALLEL_MP_AP_WORK
select PLATFORM_USES_FSP2_0
select POSTCAR_CONSOLE
select POSTCAR_STAGE
select REG_SCRIPT
select RELOCATABLE_MODULES
select RELOCATABLE_RAMSTAGE
select SMM_TSEG
select SMP
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_ACPI
select SOC_INTEL_COMMON_BLOCK_CAR
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
select SOC_INTEL_COMMON_BLOCK_CSE
select SOC_INTEL_COMMON_BLOCK_DSP
select SOC_INTEL_COMMON_BLOCK_EBDA
select SOC_INTEL_COMMON_BLOCK_FAST_SPI
select SOC_INTEL_COMMON_BLOCK_GPIO
select SOC_INTEL_COMMON_BLOCK_GRAPHICS
select SOC_INTEL_COMMON_BLOCK_GSPI
select SOC_INTEL_COMMON_BLOCK_ITSS
select SOC_INTEL_COMMON_BLOCK_I2C
select SOC_INTEL_COMMON_BLOCK_LPC
select SOC_INTEL_COMMON_BLOCK_LPSS
select SOC_INTEL_COMMON_BLOCK_P2SB
select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_PMC
select SOC_INTEL_COMMON_BLOCK_RTC
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SCS
select SOC_INTEL_COMMON_BLOCK_SMBUS
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_BLOCK_SPI
select SOC_INTEL_COMMON_BLOCK_TIMER
select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
select SOC_INTEL_COMMON_RESET
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
select UDELAY_TSC
config UART_DEBUG
bool "Enable UART debug port."
default y
select CONSOLE_SERIAL
select BOOTBLOCK_CONSOLE
select DRIVERS_UART
select DRIVERS_UART_8250MEM_32
select NO_UART_ON_SUPERIO
config UART_FOR_CONSOLE
int "Index for LPSS UART port to use for console"
default 2 if DRIVERS_UART_8250MEM_32
default 0
help
Index for LPSS UART port to use for console:
0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
config DCACHE_RAM_BASE
default 0xfef00000
config DCACHE_RAM_SIZE
default 0x40000
help
The size of the cache-as-ram region required during bootblock
and/or romstage.
config DCACHE_BSP_STACK_SIZE
hex
default 0x4000
help
The amount of anticipated stack usage in CAR by bootblock and
other stages.
config IED_REGION_SIZE
hex
default 0x400000
config MAX_ROOT_PORTS
int
default 16
config SMM_TSEG_SIZE
hex
default 0x800000
config PCR_BASE_ADDRESS
hex
default 0xfd000000
help
This option allows you to select MMIO Base Address of sideband bus.
config CPU_BCLK_MHZ
int
default 100
config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ
int
default 120
config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
int
default 3
# Clock divider parameters for 115200 baud rate
config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
hex
default 0x30
config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
hex
default 0xc35
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
config VBOOT
select VBOOT_SEPARATE_VERSTAGE
select VBOOT_OPROM_MATTERS
select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
select VBOOT_STARTS_IN_BOOTBLOCK
select VBOOT_VBNV_CMOS
select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
config C_ENV_BOOTBLOCK_SIZE
hex
default 0x4000
config STACK_SIZE
hex
default 0x2000
endif
|
