blob: ddb16198aaeffec37476eb71b65cb26fc84f6023 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
|
config SOC_INTEL_CANNONLAKE_BASE
bool
config SOC_INTEL_COFFEELAKE
bool
select SOC_INTEL_CANNONLAKE_BASE
select FSP_USES_CB_STACK
select HAVE_EXP_X86_64_SUPPORT
select HAVE_INTEL_FSP_REPO
select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
config SOC_INTEL_WHISKEYLAKE
bool
select SOC_INTEL_CANNONLAKE_BASE
select FSP_USES_CB_STACK
select HAVE_INTEL_FSP_REPO
select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
config SOC_INTEL_COMETLAKE
bool
select SOC_INTEL_CANNONLAKE_BASE
select FSP_USES_CB_STACK
select HAVE_INTEL_FSP_REPO
select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT
select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU
config SOC_INTEL_COMETLAKE_1
bool
select SOC_INTEL_COMETLAKE
config SOC_INTEL_COMETLAKE_2
bool
select SOC_INTEL_COMETLAKE
config SOC_INTEL_COMETLAKE_S
bool
select SOC_INTEL_COMETLAKE
config SOC_INTEL_COMETLAKE_V
bool
select SOC_INTEL_COMETLAKE
config SOC_INTEL_CANNONLAKE_PCH_H
bool
if SOC_INTEL_CANNONLAKE_BASE
config CPU_SPECIFIC_OPTIONS
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ACPI_NHLT
select ARCH_X86
select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS
select CPU_INTEL_COMMON
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select CPU_SUPPORTS_PM_TIMER_EMULATION
select DISPLAY_FSP_VERSION_INFO
select FSP_COMPRESS_FSP_S_LZMA
select FSP_M_XIP
select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
select GENERIC_GPIO_LIB
select HAVE_FSP_GOP
select HAVE_FSP_LOGO_SUPPORT
select HAVE_SMI_HANDLER
select IDT_IN_EVERY_STAGE
select INTEL_CAR_NEM_ENHANCED
select INTEL_DESCRIPTOR_MODE_CAPABLE
select INTEL_GMA_ACPI
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
select MRC_SETTINGS_PROTECT
select PARALLEL_MP_AP_WORK
select PLATFORM_USES_FSP2_0
select PMC_GLOBAL_RESET_ENABLE_LOCK
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_ACPI
select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
select SOC_INTEL_COMMON_BLOCK_CAR
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CNVI
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE
select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
select SOC_INTEL_COMMON_BLOCK_HDA
select SOC_INTEL_COMMON_BLOCK_IRQ
select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SCS
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV
select SOC_INTEL_COMMON_BLOCK_XHCI
select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_MONOTONIC_TIMER
select UDELAY_TSC
select UDK_2017_BINDING
select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
config MAX_CPUS
int
default 12
config DIMM_SPD_SIZE
default 512
config DCACHE_RAM_BASE
default 0xfef00000
config DCACHE_RAM_SIZE
default 0x40000
help
The size of the cache-as-ram region required during bootblock
and/or romstage.
config DCACHE_BSP_STACK_SIZE
hex
default 0x20400 if FSP_USES_CB_STACK
default 0x4000
help
The amount of anticipated stack usage in CAR by bootblock and
other stages. In the case of FSP_USES_CB_STACK default value will be
sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB).
config FSP_TEMP_RAM_SIZE
hex
depends on FSP_USES_CB_STACK
default 0x10000
help
The amount of anticipated heap usage in CAR by FSP.
Refer to Platform FSP integration guide document to know
the exact FSP requirement for Heap setup.
config IFD_CHIPSET
string
default "cnl"
config IED_REGION_SIZE
hex
default 0x400000
config HEAP_SIZE
hex
default 0x8000
config NHLT_DMIC_1CH_16B
bool
depends on ACPI_NHLT
default n
help
Include DSP firmware settings for 1 channel 16B DMIC array.
config NHLT_DMIC_2CH_16B
bool
depends on ACPI_NHLT
default n
help
Include DSP firmware settings for 2 channel 16B DMIC array.
config NHLT_DMIC_4CH_16B
bool
depends on ACPI_NHLT
default n
help
Include DSP firmware settings for 4 channel 16B DMIC array.
config NHLT_MAX98357
bool
depends on ACPI_NHLT
default n
help
Include DSP firmware settings for headset codec.
config NHLT_MAX98373
bool
depends on ACPI_NHLT
default n
help
Include DSP firmware settings for headset codec.
config NHLT_DA7219
bool
depends on ACPI_NHLT
default n
help
Include DSP firmware settings for headset codec.
config MAX_ROOT_PORTS
int
default 24 if SOC_INTEL_CANNONLAKE_PCH_H
default 16
config MAX_PCIE_CLOCK_SRC
int
default 16 if SOC_INTEL_CANNONLAKE_PCH_H
default 6
config SMM_TSEG_SIZE
hex
default 0x800000
config SMM_RESERVED_SIZE
hex
default 0x200000
config PCR_BASE_ADDRESS
hex
default 0xfd000000
help
This option allows you to select MMIO Base Address of sideband bus.
config CPU_BCLK_MHZ
int
default 100
config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
int
default 120
config CPU_XTAL_HZ
default 24000000
config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
int
default 216
config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
int
default 3
config SOC_INTEL_I2C_DEV_MAX
int
default 4 if SOC_INTEL_CANNONLAKE_PCH_H
default 6
config CONSOLE_UART_BASE_ADDRESS
hex
default 0xfe032000
depends on INTEL_LPSS_UART_FOR_CONSOLE
# Clock divider parameters for 115200 baud rate
config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
hex
default 0x30
config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
hex
default 0xc35
config VBOOT
select VBOOT_SEPARATE_VERSTAGE
select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_BOOTBLOCK
select VBOOT_VBNV_CMOS
select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
config CBFS_SIZE
default 0x200000
config MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE
bool
default n
help
Select this if the board has a SD_PWR_ENABLE pin connected to a
active high sensing load switch to turn on power to the card reader.
This will enable a workaround in ASL _PS3 and _PS0 methods to force
SD_PWR_ENABLE to stay low in D3.
config FSP_HEADER_PATH
default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE
default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/" if SOC_INTEL_COMETLAKE_1
default "3rdparty/fsp/CometLakeFspBinPkg/CometLake2/Include/" if SOC_INTEL_COMETLAKE_2
default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Include/" if SOC_INTEL_COMETLAKE_S
default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeV/Include/" if SOC_INTEL_COMETLAKE_V
config FSP_FD_PATH
default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE
default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Fsp.fd" if SOC_INTEL_COMETLAKE_1
default "3rdparty/fsp/CometLakeFspBinPkg/CometLake2/Fsp.fd" if SOC_INTEL_COMETLAKE_2
default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Fsp.fd" if SOC_INTEL_COMETLAKE_S
default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeV/Fsp.fd" if SOC_INTEL_COMETLAKE_V
config SOC_INTEL_CANNONLAKE_DEBUG_CONSENT
int "Debug Consent for CNL"
# USB DBC is more common for developers so make this default to 3 if
# SOC_INTEL_DEBUG_CONSENT=y
default 3 if SOC_INTEL_DEBUG_CONSENT
default 0
help
This is to control debug interface on SOC.
Setting non-zero value will allow to use DBC or DCI to debug SOC.
PlatformDebugConsent in FspmUpd.h has the details.
config PRERAM_CBMEM_CONSOLE_SIZE
hex
default 0xe00
config INTEL_TXT_BIOSACM_ALIGNMENT
hex
default 0x40000 # 256KB
config INTEL_GMA_BCLV_OFFSET
default 0xc8258
config INTEL_GMA_BCLV_WIDTH
default 32
config INTEL_GMA_BCLM_OFFSET
default 0xc8254
config INTEL_GMA_BCLM_WIDTH
default 32
endif
|