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## SPDX-License-Identifier: GPL-2.0-only
config SOC_INTEL_BAYTRAIL
bool
select ACPI_COMMON_MADT_IOAPIC
select ACPI_COMMON_MADT_LAPIC
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ARCH_X86
select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS
select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
select SUPPORT_CPU_UCODE_IN_CBFS
select HAVE_SMI_HANDLER
select SOUTHBRIDGE_INTEL_COMMON_RESET
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
select REG_SCRIPT
select RTC
select SPI_FLASH
select SSE2
select TSC_MONOTONIC_TIMER
select TSC_SYNC_MFENCE
select UDELAY_TSC
select SOC_INTEL_COMMON
select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT
select INTEL_GMA_ACPI
select INTEL_GMA_SWSMISCI
select CPU_INTEL_COMMON
select CPU_HAS_L2_ENABLE_MSR
select TCO_SPACE_NOT_YET_SPLIT
select USE_DDR3
select NEED_SMALL_2MB_PAGE_TABLES
help
Bay Trail M/D part support.
if SOC_INTEL_BAYTRAIL
config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_ROMSTAGE
config ECAM_MMCONF_BASE_ADDRESS
default 0xe0000000
config ECAM_MMCONF_BUS_NUMBER
int
default 256
config MAX_CPUS
int
default 4
config SMM_TSEG_SIZE
hex
default 0x800000
config SMM_RESERVED_SIZE
hex
default 0x100000
config HAVE_MRC
bool "Add a System Agent binary"
help
Select this option to add a System Agent binary to
the resulting coreboot image.
Note: Without this binary coreboot will not work
config MRC_FILE
string "Intel System Agent path and filename"
depends on HAVE_MRC
default "mrc.bin"
help
The path and filename of the file to use as System Agent
binary.
config MRC_BIN_ADDRESS
hex
default 0xfffa0000
config MRC_RMT
bool "Enable MRC RMT training + debug prints"
default n
# Cache As RAM region layout:
#
# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE
# | MRC usage |
# | |
# -------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE
# | coreboot |
# | usage |
# +-------------+ DCACHE_RAM_BASE
#
# Note that the MRC binary is linked to assume the region marked as "MRC usage"
# starts at DCACHE_RAM_BASE + DCACHE_RAM_SIZE. If those values change then
# a new MRC binary needs to be produced with the updated start and size
# information.
config DCACHE_RAM_BASE
hex
default 0xfe000000
config DCACHE_RAM_SIZE
hex
default 0x8000
help
The size of the cache-as-ram region required during bootblock
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
must add up to a power of 2.
config PRERAM_CBFS_CACHE_SIZE
default 0x0
config DCACHE_RAM_MRC_VAR_SIZE
hex
default 0x8000
help
The amount of cache-as-ram region required by the reference code.
config DCACHE_BSP_STACK_SIZE
hex
default 0x2000
config ENABLE_BUILTIN_COM1
bool "Enable builtin COM1 Serial Port"
default n
help
The PMC has a legacy COM1 serial port. Choose this option to
configure the pads and enable it. This serial port can be used for
the debug console.
config HAVE_REFCODE_BLOB
depends on ARCH_X86
bool "Use a binary refcode blob instead of native ModPHY init"
default n
help
Use the ChromeBook refcode to initialize high-speed PHYs instead of
native code.
if HAVE_REFCODE_BLOB
# Ask for the blob if the user wants it
config REFCODE_BLOB_FILE
string "Path and filename to reference code blob."
default "refcode.elf"
help
The path and filename to the file to be added to cbfs.
endif # HAVE_REFCODE_BLOB
config VGA_BIOS_ID
string
depends on VGA_BIOS
default "8086,0f31"
endif
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