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/*
* This file is part of the coreboot project.
*
* Copyright 2019 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <intelblocks/xhci.h>
#define XHCI_USB2_PORT_STATUS_REG 0x480
#if CONFIG(SOC_INTEL_GLK)
#define XHCI_USB3_PORT_STATUS_REG 0x510
#define XHCI_USB2_PORT_NUM 9
#else
#define XHCI_USB3_PORT_STATUS_REG 0x500
#define XHCI_USB2_PORT_NUM 8
#endif
#define XHCI_USB3_PORT_NUM 7
static const struct xhci_usb_info usb_info = {
.usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG,
.num_usb2_ports = XHCI_USB2_PORT_NUM,
.usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG,
.num_usb3_ports = XHCI_USB3_PORT_NUM,
};
const struct xhci_usb_info *soc_get_xhci_usb_info(void)
{
return &usb_info;
}
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