blob: cccbffd40dbd0fe6f356b8726c41d0d2503fa3cb (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Intel Corp.
* (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* The device_t returned by dev_find_slot() is different than the device_t
* passed to pci_write_config32(). If one needs to get access to the config.h
* of a device and perform i/o things are incorrect. One is a pointer while
* the other is a 32-bit integer.
*/
#define __SIMPLE_DEVICE__
#include <arch/io.h>
#include <assert.h>
#include <cbmem.h>
#include <device/pci.h>
#include <soc/northbridge.h>
#include <soc/pci_devs.h>
#include <soc/smm.h>
static uintptr_t smm_region_start(void)
{
return ALIGN_DOWN(pci_read_config32(NB_DEV_ROOT, TSEG), 1*MiB);
}
static size_t smm_region_size(void)
{
uintptr_t smm_end =
ALIGN_DOWN(pci_read_config32(NB_DEV_ROOT, BGSM), 1*MiB);
return smm_end - smm_region_start();
}
void *cbmem_top(void)
{
return (void *)smm_region_start();
}
void smm_region(void **start, size_t *size)
{
*start = (void *)smm_region_start();
*size = smm_region_size();
}
int smm_subregion(int sub, void **start, size_t *size)
{
uintptr_t sub_base;
size_t sub_size;
const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
sub_base = smm_region_start();
sub_size = smm_region_size();
assert(sub_size > CONFIG_SMM_RESERVED_SIZE);
switch (sub) {
case SMM_SUBREGION_HANDLER:
/* Handler starts at the base of TSEG. */
sub_size -= cache_size;
break;
case SMM_SUBREGION_CACHE:
/* External cache is in the middle of TSEG. */
sub_base += sub_size - cache_size;
sub_size = cache_size;
break;
default:
return -1;
}
*start = (void *)sub_base;
*size = sub_size;
return 0;
}
|
