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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Intel Corp.
* (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <arch/cpu.h>
#include <bootblock_common.h>
#include <device/pci.h>
#include <soc/bootblock.h>
#include <soc/cpu.h>
#include <soc/northbridge.h>
#include <soc/pci_devs.h>
#include <soc/uart.h>
void asmlinkage bootblock_c_entry(void)
{
device_t dev = NB_DEV_ROOT;
/* Set PCI Express BAR */
pci_io_write_config32(dev, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1);
dev = P2SB_DEV;
/* BAR and MMIO enable for IOSF, so that GPIOs can be configured */
pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_IOSF_BASE_ADDRESS);
pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
/* Call lib/bootblock.c main */
main();
}
void bootblock_soc_early_init(void)
{
/* Prepare UART for serial console. */
if (IS_ENABLED(CONFIG_SOC_UART_DEBUG))
soc_console_uart_init();
}
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