summaryrefslogtreecommitdiff
path: root/src/soc/intel/apollolake/Kconfig
blob: b37cde678f68d097a507430171b0eb9d54ff9e93 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
config SOC_INTEL_APOLLOLAKE
	bool
	help
	  Intel Apollolake support

if SOC_INTEL_APOLLOLAKE

config CPU_SPECIFIC_OPTIONS
	def_bool y
	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
	select ARCH_BOOTBLOCK_X86_32
	select ARCH_RAMSTAGE_X86_32
	select ARCH_ROMSTAGE_X86_32
	select ARCH_VERSTAGE_X86_32
	select BOOTBLOCK_CONSOLE
	select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
	select BOOT_DEVICE_SUPPORTS_WRITES
	# CPU specific options
	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
	select IOAPIC
	select SMP
	select SSE2
	select SUPPORT_CPU_UCODE_IN_CBFS
	# Audio options
	select ACPI_NHLT
	select SOC_INTEL_COMMON_NHLT
	# Misc options
	select C_ENVIRONMENT_BOOTBLOCK
	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
	select COLLECT_TIMESTAMPS
	select COMMON_FADT
	select GENERIC_GPIO_LIB
	select HAVE_INTEL_FIRMWARE
	select HAVE_SMI_HANDLER
	select MRC_SETTINGS_PROTECT
	select NO_FIXED_XIP_ROM_SIZE
	select NO_XIP_EARLY_STAGES
	select PARALLEL_MP
	select PARALLEL_MP_AP_WORK
	select PCIEXP_ASPM
	select PCIEXP_COMMON_CLOCK
	select PCIEXP_CLK_PM
	select PCIEXP_L1_SUB_STATE
	select POSTCAR_CONSOLE
	select POSTCAR_STAGE
	select REG_SCRIPT
	select RELOCATABLE_RAMSTAGE	# Build fails if this is not selected
	select RTC
	select SMM_TSEG
	select SOC_INTEL_COMMON
	select SOC_INTEL_COMMON_ACPI
	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
	select SOC_INTEL_COMMON_LPSS_I2C
	select SOC_INTEL_COMMON_SMI
	select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
	select UDELAY_TSC
	select TSC_CONSTANT_RATE
	select TSC_MONOTONIC_TIMER
	select HAVE_MONOTONIC_TIMER
	select PLATFORM_USES_FSP2_0
	select HAVE_HARD_RESET
	select SOC_INTEL_COMMON
	select SOC_INTEL_COMMON_GFX_OPREGION
	select ADD_VBT_DATA_FILE

config CHROMEOS
	select CHROMEOS_RAMOOPS_DYNAMIC
	select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC
	select SEPARATE_VERSTAGE
	select VBOOT_OPROM_MATTERS
	select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
	select VBOOT_STARTS_IN_BOOTBLOCK
	select VBOOT_VBNV_CMOS
	select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
	select VIRTUAL_DEV_SWITCH

config TPM_ON_FAST_SPI
	bool
	default n
	select LPC_TPM
	help
	 TPM part is conntected on Fast SPI interface, but the LPC MMIO
	 TPM transactions are decoded and serialized over the SPI interface.

config SOC_INTEL_COMMON_RESET
	bool
	default y

config MMCONF_BASE_ADDRESS
	hex "PCI MMIO Base Address"
	default 0xe0000000

config IOSF_BASE_ADDRESS
	hex "MMIO Base Address of sideband bus"
	default 0xd0000000

config DCACHE_RAM_BASE
	hex "Base address of cache-as-RAM"
	default 0xfef00000

config DCACHE_RAM_SIZE
	hex "Length in bytes of cache-as-RAM"
	default 0xc0000
	help
	  The size of the cache-as-ram region required during bootblock
	  and/or romstage.

config DCACHE_BSP_STACK_SIZE
	hex
	default 0x4000
	help
	  The amount of anticipated stack usage in CAR by bootblock and
	  other stages.

config CPU_ADDR_BITS
	int
	default 36

config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ
	depends on SOC_INTEL_COMMON_LPSS_I2C
	int
	default 133

config CONSOLE_UART_BASE_ADDRESS
	depends on CONSOLE_SERIAL
	hex "MMIO base address for UART"
	default 0xde000000

config SOC_UART_DEBUG
	bool "Enable SoC UART debug port selected by UART_FOR_CONSOLE."
	default n
	select CONSOLE_SERIAL
	select DRIVERS_UART
	select DRIVERS_UART_8250MEM_32
	select NO_UART_ON_SUPERIO

# 32KiB bootblock is all that is mapped in by the CSE at top of 4GiB.
config C_ENV_BOOTBLOCK_SIZE
	hex
	default 0x8000

# This SoC does not map SPI flash like many previous SoC. Therefore we provide
# a custom media driver that facilitates mapping
config X86_TOP4G_BOOTMEDIA_MAP
	bool
	default n

config ROMSTAGE_ADDR
	hex
	default 0xfef20000
	help
	  The base address (in CAR) where romstage should be linked

config VERSTAGE_ADDR
	hex
	default 0xfef40000
	help
	  The base address (in CAR) where verstage should be linked

config CACHE_MRC_SETTINGS
	bool
	default y

config MRC_SETTINGS_VARIABLE_DATA
	bool
	default y

config FSP_M_ADDR
	hex
	default 0xfef40000
	help
	  The address FSP-M will be relocated to during build time

config NEED_LBP2
	bool "Write contents for logical boot partition 2."
	default n
	help
	  Write the contents from a file into the logical boot partition 2
	  region defined by LBP2_FMAP_NAME.

config LBP2_FMAP_NAME
	string "Name of FMAP region to put logical boot partition 2"
	depends on NEED_LBP2
	default "SIGN_CSE"
	help
	  Name of FMAP region to write logical boot partition 2 data.

config LBP2_FILE_NAME
	string "Path of file to write to logical boot partition 2 region"
	depends on NEED_LBP2
	default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/lbp2.bin"
	help
	  Name of file to store in the logical boot partition 2 region.

config NEED_IFWI
	bool "Write content into IFWI region"
	default n
	help
	  Write the content from a file into IFWI region defined by
	  IFWI_FMAP_NAME.

config IFWI_FMAP_NAME
	string "Name of FMAP region to pull IFWI into"
	depends on NEED_IFWI
	default "IFWI"
	help
	  Name of FMAP region to write IFWI.

config IFWI_FILE_NAME
	string "Path of file to write to IFWI region"
	depends on NEED_IFWI
	default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ifwi.bin"
	help
	  Name of file to store in the IFWI region.

config HEAP_SIZE
	hex
	default 0x8000

config NHLT_DMIC_1CH_16B
	bool
	depends on ACPI_NHLT
	default n
	help
	  Include DSP firmware settings for 1 channel 16B DMIC array.

config NHLT_DMIC_2CH_16B
	bool
	depends on ACPI_NHLT
	default n
	help
	  Include DSP firmware settings for 2 channel 16B DMIC array.

config NHLT_DMIC_4CH_16B
	bool
	depends on ACPI_NHLT
	default n
	help
	  Include DSP firmware settings for 4 channel 16B DMIC array.

config NHLT_MAX98357
	bool
	depends on ACPI_NHLT
	default n
	help
	  Include DSP firmware settings for headset codec.

config NHLT_DA7219
	bool
	depends on ACPI_NHLT
	default n
	help
	  Include DSP firmware settings for headset codec.
choice
	prompt "Cache-as-ram implementation"
	default CAR_CQOS
	help
	  This option allows you to select how cache-as-ram (CAR) is set up.

config CAR_NEM
	bool "Non-evict mode"
	help
	  Traditionally, CAR is set up by using Non-Evict mode. This method
	  does not allow CAR and cache to co-exist, because cache fills are
	  block in NEM mode.

config CAR_CQOS
	bool "Cache Quality of Service"
	help
	  Cache Quality of Service allows more fine-grained control of cache
	  usage. As result, it is possible to set up portion of L2 cache for
	  CAR and use remainder for actual caching.

endchoice

config SPI_FLASH_INCLUDE_ALL_DRIVERS
	bool
	default n

config SMM_RESERVED_SIZE
	hex
	default 0x100000

config IFD_CHIPSET
	string
	default "aplk"

endif