1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
|
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _SOC_CHIP_H_
#define _SOC_CHIP_H_
#include <drivers/i2c/designware/dw_i2c.h>
#include <intelblocks/cfg.h>
#include <intelblocks/gpio.h>
#include <intelblocks/gspi.h>
#include <intelblocks/power_limit.h>
#include <intelblocks/pcie_rp.h>
#include <intelblocks/tcss.h>
#include <soc/gpe.h>
#include <soc/pci_devs.h>
#include <soc/pmc.h>
#include <soc/serialio.h>
#include <soc/usb.h>
#include <stdint.h>
#define MAX_HD_AUDIO_DMIC_LINKS 2
#define MAX_HD_AUDIO_SNDW_LINKS 4
#define MAX_HD_AUDIO_SSP_LINKS 6
struct soc_intel_alderlake_config {
/* Common struct containing soc config data required by common code */
struct soc_intel_common_config common_soc_config;
/* Common struct containing power limits configuration information */
struct soc_power_limits_config power_limits_config;
/* Gpio group routed to each dword of the GPE0 block. Values are
* of the form PMC_GPP_[A:U] or GPD. */
uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */
uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */
uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */
/* Generic IO decode ranges */
uint32_t gen1_dec;
uint32_t gen2_dec;
uint32_t gen3_dec;
uint32_t gen4_dec;
/* Enable S0iX support */
int s0ix_enable;
/* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */
uint8_t TcssD3HotDisable;
/* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */
uint8_t TcssD3ColdDisable;
/* Enable DPTF support */
int dptf_enable;
/* Deep SX enable for both AC and DC */
int deep_s3_enable_ac;
int deep_s3_enable_dc;
int deep_s5_enable_ac;
int deep_s5_enable_dc;
/* Deep Sx Configuration
* DSX_EN_WAKE_PIN - Enable WAKE# pin
* DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin
* DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */
uint32_t deep_sx_config;
/* TCC activation offset */
uint32_t tcc_offset;
/* System Agent dynamic frequency support. Only effects ULX/ULT CPUs.
* When enabled memory will be training at two different frequencies.
* 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2,
* 4:FixedPoint3, 5:Enabled */
enum {
SaGv_Disabled,
SaGv_FixedPoint0,
SaGv_FixedPoint1,
SaGv_FixedPoint2,
SaGv_FixedPoint3,
SaGv_Enabled,
} SaGv;
/* Rank Margin Tool. 1:Enable, 0:Disable */
uint8_t RMT;
/* USB related */
struct usb2_port_config usb2_ports[16];
struct usb3_port_config usb3_ports[10];
/* Wake Enable Bitmap for USB2 ports */
uint16_t usb2_wake_enable_bitmap;
/* Wake Enable Bitmap for USB3 ports */
uint16_t usb3_wake_enable_bitmap;
/* Program OC pins for TCSS */
struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS];
/* SATA related */
uint8_t SataEnable;
uint8_t SataMode;
uint8_t SataSalpSupport;
uint8_t SataPortsEnable[8];
uint8_t SataPortsDevSlp[8];
/*
* Enable(0)/Disable(1) SATA Power Optimizer on PCH side.
* Default 0. Setting this to 1 disables the SATA Power Optimizer.
*/
uint8_t SataPwrOptimizeDisable;
/*
* SATA Port Enable Dito Config.
* Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
*/
uint8_t SataPortsEnableDitoConfig[8];
/* SataPortsDmVal is the DITO multiplier. Default is 15. */
uint8_t SataPortsDmVal[8];
/* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */
uint16_t SataPortsDitoVal[8];
/* Audio related */
uint8_t PchHdaDspEnable;
uint8_t PchHdaAudioLinkHdaEnable;
uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS];
uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS];
uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS];
uint8_t PchHdaIDispLinkTmode;
uint8_t PchHdaIDispLinkFrequency;
uint8_t PchHdaIDispCodecDisconnect;
struct pcie_rp_config pch_pcie_rp[CONFIG_MAX_PCH_ROOT_PORTS];
struct pcie_rp_config cpu_pcie_rp[CONFIG_MAX_CPU_ROOT_PORTS];
uint8_t pcie_clk_config_flag[CONFIG_MAX_PCIE_CLOCK_SRC];
/* Gfx related */
enum {
IGD_SM_0MB = 0x00,
IGD_SM_32MB = 0x01,
IGD_SM_64MB = 0x02,
IGD_SM_96MB = 0x03,
IGD_SM_128MB = 0x04,
IGD_SM_160MB = 0x05,
IGD_SM_4MB = 0xF0,
IGD_SM_8MB = 0xF1,
IGD_SM_12MB = 0xF2,
IGD_SM_16MB = 0xF3,
IGD_SM_20MB = 0xF4,
IGD_SM_24MB = 0xF5,
IGD_SM_28MB = 0xF6,
IGD_SM_36MB = 0xF8,
IGD_SM_40MB = 0xF9,
IGD_SM_44MB = 0xFA,
IGD_SM_48MB = 0xFB,
IGD_SM_52MB = 0xFC,
IGD_SM_56MB = 0xFD,
IGD_SM_60MB = 0xFE,
} IgdDvmt50PreAlloc;
uint8_t SkipExtGfxScan;
/* HeciEnabled decides the state of Heci1 at end of boot
* Setting to 0 (default) disables Heci1 and hides the device from OS */
uint8_t HeciEnabled;
/* PL2 Override value in Watts */
uint32_t tdp_pl2_override;
/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
uint8_t eist_enable;
/* Enable C6 DRAM */
uint8_t enable_c6dram;
/*
* PRMRR size setting with below options
* Disable: 0x0
* 32MB: 0x2000000
* 64MB: 0x4000000
* 128 MB: 0x8000000
* 256 MB: 0x10000000
* 512 MB: 0x20000000
*/
uint32_t PrmrrSize;
uint8_t PmTimerDisabled;
/*
* SerialIO device mode selection:
* PchSerialIoDisabled,
* PchSerialIoPci,
* PchSerialIoHidden,
* PchSerialIoLegacyUart,
* PchSerialIoSkipInit
*/
uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX];
uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX];
/*
* GSPIn Default Chip Select Mode:
* 0:Hardware Mode,
* 1:Software Mode
*/
uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
/*
* GSPIn Default Chip Select State:
* 0: Low,
* 1: High
*/
uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
/* Debug interface selection */
enum {
DEBUG_INTERFACE_RAM = (1 << 0),
DEBUG_INTERFACE_UART_8250IO = (1 << 1),
DEBUG_INTERFACE_USB3 = (1 << 3),
DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4),
DEBUG_INTERFACE_TRACEHUB = (1 << 5),
} debug_interface_flag;
/* Enable Pch iSCLK */
uint8_t pch_isclk;
/* CNVi BT Core Enable/Disable */
bool CnviBtCore;
/* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
bool CnviBtAudioOffload;
/*
* IOM Port Config
* If a port orientation needs to be controlled by the SOC this setting must be
* updated to reflect the correct GPIOs being used for the SOC port flipping.
* There are 4 ports each with a pair of GPIOs for Pull Up and Pull Down
* 0,1 are pull up and pull down for port 0
* 2,3 are pull up and pull down for port 1
* 4,5 are pull up and pull down for port 2
* 6,7 are pull up and pull down for port 3
* values to be programmed correspond to the GPIO family and offsets
*/
uint32_t IomTypeCPortPadCfg[8];
/*
* SOC Aux orientation override:
* This is a bitfield that corresponds to up to 4 TCSS ports on ADL.
* Even numbered bits (0, 2, 4, 6) control the retimer being handled by SOC.
* Odd numbered bits (1, 3, 5, 7) control the orientation of the physical aux lines
* on the motherboard.
*/
uint16_t TcssAuxOri;
/* Connect Topology Command timeout value */
uint16_t ITbtConnectTopologyTimeoutInMs;
/*
* Override GPIO PM configuration:
* 0: Use FSP default GPIO PM program,
* 1: coreboot to override GPIO PM program
*/
uint8_t gpio_override_pm;
/*
* GPIO PM configuration: 0 to disable, 1 to enable power gating
* Bit 6-7: Reserved
* Bit 5: MISCCFG_GPSIDEDPCGEN
* Bit 4: MISCCFG_GPRCOMPCDLCGEN
* Bit 3: MISCCFG_GPRTCDLCGEN
* Bit 2: MISCCFG_GSXLCGEN
* Bit 1: MISCCFG_GPDPCGEN
* Bit 0: MISCCFG_GPDLCGEN
*/
uint8_t gpio_pm[TOTAL_GPIO_COMM];
/* DP config */
/*
* Port config
* 0:Disabled, 1:eDP, 2:MIPI DSI
*/
uint8_t DdiPortAConfig;
uint8_t DdiPortBConfig;
/* Enable(1)/Disable(0) HPD */
uint8_t DdiPortAHpd;
uint8_t DdiPortBHpd;
uint8_t DdiPortCHpd;
uint8_t DdiPort1Hpd;
uint8_t DdiPort2Hpd;
uint8_t DdiPort3Hpd;
uint8_t DdiPort4Hpd;
/* Enable(1)/Disable(0) DDC */
uint8_t DdiPortADdc;
uint8_t DdiPortBDdc;
uint8_t DdiPortCDdc;
uint8_t DdiPort1Ddc;
uint8_t DdiPort2Ddc;
uint8_t DdiPort3Ddc;
uint8_t DdiPort4Ddc;
/* Hybrid storage mode enable (1) / disable (0)
* This mode makes FSP detect Optane and NVME and set PCIe lane mode
* accordingly */
uint8_t HybridStorageMode;
/*
* Override CPU flex ratio value:
* CPU ratio value controls the maximum processor non-turbo ratio.
* Valid Range 0 to 63.
*
* In general descriptor provides option to set default cpu flex ratio.
* Default cpu flex ratio is 0 ensures booting with non-turbo max frequency.
* That's the reason FSP skips cpu_ratio override if cpu_ratio is 0.
*
* Only override CPU flex ratio if don't want to boot with non-turbo max.
*/
uint8_t cpu_ratio_override;
/*
* Enable(0)/Disable(1) DMI Power Optimizer on PCH side.
* Default 0. Setting this to 1 disables the DMI Power Optimizer.
*/
uint8_t DmiPwrOptimizeDisable;
/*
* Enable(1)/Disable(0) CPU Replacement check.
* Default 0. Setting this to 1 to check CPU replacement.
*/
uint8_t CpuReplacementCheck;
/* ISA Serial Base selection. */
enum {
ISA_SERIAL_BASE_ADDR_3F8,
ISA_SERIAL_BASE_ADDR_2F8,
} IsaSerialUartBase;
};
typedef struct soc_intel_alderlake_config config_t;
#endif
|