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path: root/src/soc/cavium/cn81xx/include/soc/memlayout.ld
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/*
 * This file is part of the coreboot project.
 *
 * Copyright 2016 Rockchip Inc.
 * Copyright 2017-present Facebook, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <memlayout.h>
#include <soc/addressmap.h>
#include <arch/header.ld>

SECTIONS
{
	DRAM_START(0x00000000)
	/* Secure region 0 - 1MiB */
	BL31(0, 0xe0000)
	REGION(sff8104, 0xe0000, 0x20000, 0x1000)

	/* Insecure region 1MiB - TOP OF DRAM */
	/* bootblock-custom.S does setup CAR from SRAM_START to SRAM_END */
	SRAM_START(BOOTROM_OFFSET)

	STACK(BOOTROM_OFFSET, 16K)
	TIMESTAMP(BOOTROM_OFFSET + 0x4000, 4K)
	PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 8K)
	PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K)
	BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K)
	VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K)
	VBOOT2_TPM_LOG(BOOTROM_OFFSET + 0x33000, 2K)
	VERSTAGE(BOOTROM_OFFSET + 0x33800, 50K)
	ROMSTAGE(BOOTROM_OFFSET + 0x40000, 256K)

	SRAM_END(BOOTROM_OFFSET + 0x80000)

	TTB(BOOTROM_OFFSET + 0x80000, 512K)
	RAMSTAGE(BOOTROM_OFFSET + 0x100000, 512K)
	/* Stack for secondary CPUs */
	REGION(stack_sec, BOOTROM_OFFSET + 0x180000,
	       CONFIG_MAX_CPUS * CONFIG_STACK_SIZE, 0x1000)

	/* Leave some space for the payload */
	POSTRAM_CBFS_CACHE(0x2000000, 16M)
}