blob: 00b4f6c7137df82b26cae550248d9ac913b23b2f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
|
/*
* Copyright (C) 2015 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SOC_BROADCOM_CYGNUS_SHMOO_AND28_H__
#define __SOC_BROADCOM_CYGNUS_SHMOO_AND28_H__
#include <delay.h>
#include <soc/cygnus_types.h>
#undef printf
#if IS_ENABLED(CONFIG_CYGNUS_PRINT_SHMOO_DEBUG)
#include <console/console.h>
#define printf(args...) printk(BIOS_INFO, args)
#else
#define printf(args...)
#endif
#ifndef SOC_E_NONE
#define SOC_E_NONE 0x0
#endif
#ifndef SOC_E_FAIL
#define SOC_E_FAIL 0x1
#endif
#ifndef SOC_E_TIMEOUT
#define SOC_E_TIMEOUT 0x2
#endif
#ifndef SOC_E_MEMORY
#define SOC_E_MEMORY 0x4
#endif
#define SET_ADDR_VDL_FORCE(v) (0x10000 | ((v) & 0x011FF))
#define SET_VREF_DAC_CONTROL(v) ((v) & 0xFFFFF)
#define SET_WR_VDL_FORCE(v) (0x10000 | ((v) & 0x011FF))
#define SET_WR_CHAN_DLY_CYC_FORCE(v) (0x10000 | ((v) & 0x000F7))
#define SET_RD_VDL_FORCE(v) (0x10000 | ((v) & 0x010FF))
#define SET_RD_EN_DLY_CYC_FORCE(v) (0x10000 | ((v) & 0x001FF))
#define SET_RD_CONTROL(v) ((v) & 0x0001F)
#define SHMOO_AND28_PHY_TYPE_RSVP 0
#define SHMOO_AND28_PHY_TYPE_E0 0xE0
#define SHMOO_AND28_PHY_TYPE_E2 0xE2
#define SHMOO_AND28_PHY_TYPE_F0 0xF0
#define SHMOO_AND28_CTL_TYPE_RSVP 0
#define SHMOO_AND28_CTL_TYPE_RSVP_STR "t0"
#define SHMOO_AND28_CTL_TYPE_1 1
#define SHMOO_AND28_CTL_TYPE_1_STR "t1"
#define SHMOO_AND28_DRAM_TYPE_RSVP 0
#define SHMOO_AND28_DRAM_TYPE_DDR3 3
#define SHMOO_AND28_DRAM_TYPE_DDR3L 31
#define SHMOO_AND28_DRAM_TYPE_DDR4 4
#define SHMOO_AND28_DRAM_TYPE_GDDR5 5
#define SHMOO_AND28_PHY_REG_BASE_RSVP 0
#define SHMOO_AND28_PHY_REG_BASE_CYGNUS 0x18011000
#define SHMOO_AND28_PHY_REG_BASE_GREYHOUND 0x18011000
#define SHMOO_AND28_YDC_DDR_BIST_REG_BASE_RSVP 0
#define SHMOO_AND28_YDC_DDR_BIST_REG_BASE_GREYHOUND 0x18010C00
#define SHMOO_AND28_CHIP_ID_RSVP 0
#define SHMOO_AND28_CHIP_ID_CYGNUS 0xC
#define SHMOO_AND28_CHIP_ID_GREYHOUND 0x6
#define SHMOO_AND28_CHIP_ID SHMOO_AND28_CHIP_ID_CYGNUS
#define SHMOO_AND28_PHY_TYPE SHMOO_AND28_PHY_TYPE_E2
#define SHMOO_AND28_PHY_REG_BASE SHMOO_AND28_PHY_REG_BASE_CYGNUS
#define SHMOO_AND28_YDC_DDR_BIST_REG_BASE SHMOO_AND28_YDC_DDR_BIST_REG_BASE_CYGNUS
#define SHMOO_AND28_CTL_TYPE SHMOO_AND28_CTL_TYPE_1
#define SHMOO_AND28_DRAM_TYPE SHMOO_AND28_DRAM_TYPE_DDR3L
#define SHMOO_AND28_PHY_BITWIDTH 16
#define SHMOO_AND28_PHY_CONSTANT_CONFIG 0
#define PHY_AND28_E2 SHMOO_AND28_PHY_TYPE
#define SHMOO_AND28_PHY_BITWIDTH_IS_32 (SHMOO_AND28_PHY_BITWIDTH >> 5)
#define YDC_DDR_BIST_PHY_BITWIDTH_IS_32 SHMOO_AND28_PHY_BITWIDTH_IS_32
#define YDC_DDR_BIST_REG_BASE SHMOO_AND28_YDC_DDR_BIST_REG_BASE
#define SHMOO_AND28_BIT 1
#define SHMOO_AND28_BYTE (SHMOO_AND28_BIT << 3)
#define SHMOO_AND28_HALFWORD (SHMOO_AND28_BYTE << 1)
#define SHMOO_AND28_WORD (SHMOO_AND28_HALFWORD << 1)
#define SHMOO_AND28_DOUBLEWORD (SHMOO_AND28_WORD << 1)
#define SHMOO_AND28_QUADWORD (SHMOO_AND28_DOUBLEWORD << 1)
#define SHMOO_AND28_SHORT_SLEEP 1
#define SHMOO_AND28_LONG_SLEEP 10
#define SHMOO_AND28_DEEP_SLEEP 100
#define SHMOO_AND28_HIBERNATION 1000
#define SHMOO_AND28_STASIS 1000000
#define SHMOO_AND28_SHMOO_RSVP -1
#define SHMOO_AND28_RD_EN 23
#define SHMOO_AND28_RD_EXTENDED 50
#define SHMOO_AND28_WR_EXTENDED 60
#define SHMOO_AND28_ADDR_EXTENDED 71
#define SHMOO_AND28_CTRL_EXTENDED 72
#define SHMOO_AND28_DDR3_SEQUENCE_COUNT 5
#define SHMOO_AND28_DDR3L_SEQUENCE_COUNT 5
/* BEGIN: EXTRA */
/* END: EXTRA */
#define SHMOO_AND28_QUICK_SHMOO_CTRL_EXTENDED 1
#define SHMOO_AND28_REPEAT 9
#define SHMOO_AND28_REPEAT_HALF (SHMOO_COMBO28_REPEAT >> 1)
#define SHMOO_AND28_SEQUENTIAL 0
#define SHMOO_AND28_SINGLE 1
#define SHMOO_AND28_ACTION_RSVP -1
#define SHMOO_AND28_ACTION_RESTORE 0
#define SHMOO_AND28_ACTION_RUN 1
#define SHMOO_AND28_ACTION_SAVE 2
#define SHMOO_AND28_ACTION_RUN_AND_SAVE 3
#define SHMOO_AND28_MAX_INTERFACES 8
#define SHMOO_AND28_INTERFACE_RSVP -1
#define SHMOO_AND28_BYTES_PER_INTERFACE 4
#define SHMOO_AND28_BIST_NOF_PATTERNS 8
#define SHMOO_AND28_BIST_MPR_NOF_PATTERNS 4
#define SHMOO_AND28_MAX_VISIBLE_UI_COUNT 4
#define SHMOO_AND28_MAX_EFFECTIVE_UI_COUNT 4
#define SHMOO_AND28_LAST_EFFECTIVE_UI (SHMOO_AND28_MAX_EFFECTIVE_UI_COUNT - 1)
#define SHMOO_AND28_MAX_VDL_LENGTH 256
#define SHMOO_AND28_MAX_VREF_RANGE 64
#define SHMOO_AND28_MAX_ZQ_CAL_RANGE 32
#define SHMOO_AND28_RESULT2D_X SHMOO_AND28_MAX_VDL_LENGTH
#define SHMOO_AND28_RESULT2D_Y SHMOO_AND28_MAX_VREF_RANGE
#define SHMOO_AND28_STRING_LENGTH (SHMOO_AND28_RESULT2D_X + 1)
#define SHMOO_AND28_ERROR_ARRAY_LENGTH 4
#define SHMOO_AND28_CALIB_CENTER_PASS 111
#define SHMOO_AND28_CALIB_RISING_EDGE 011
#define SHMOO_AND28_CALIB_FALLING_EDGE 100
#define SHMOO_AND28_CALIB_PASS_START 001
#define SHMOO_AND28_CALIB_FAIL_START 110
#define SHMOO_AND28_CALIB_VDL_ZERO 000
#define SHMOO_AND28_VDL_TFIX 18
#define SHMOO_AND28_RD_DATA_DLY_INIT 7
#define SHMOO_AND28_RD_EN_CYC_INIT 1
#define SHMOO_AND28_RD_EN_VDL_INIT 0
#define SHMOO_AND28_RD_DQ_VDL_INIT 0
#define SHMOO_AND28_RD_DQ_FAIL_CAP 5
#define SHMOO_AND28_RD_DQS_VDL_OFFSET SHMOO_AND28_RD_DQ_VDL_INIT
#define SHMOO_AND28_WR_CYC_INIT 0
#define SHMOO_AND28_PHY_NOF_AD 16
#define SHMOO_AND28_PHY_NOF_BA 3
#define SHMOO_AND28_PHY_NOF_AUX 3
#define SHMOO_AND28_PHY_NOF_CS 2
typedef struct and28_shmoo_dram_info_s {
uint32 ctl_type;
uint32 dram_type;
uint32 dram_bitmap;
uint32 interface_bitwidth;
int num_columns;
int num_rows;
int num_banks;
int data_rate_mbps;
int ref_clk_mhz;
uint32 refi;
uint32 command_parity_latency;
int sim_system_mode;
} and28_shmoo_dram_info_t;
typedef struct and28_shmoo_config_param_s {
uint16 control_regs_ad[SHMOO_AND28_PHY_NOF_AD];
uint16 control_regs_ba[SHMOO_AND28_PHY_NOF_BA];
uint16 control_regs_aux[SHMOO_AND28_PHY_NOF_AUX];
uint16 control_regs_cs[SHMOO_AND28_PHY_NOF_CS];
uint16 control_regs_par;
uint16 control_regs_ras_n;
uint16 control_regs_cas_n;
uint16 control_regs_cke;
uint16 control_regs_rst_n;
uint16 control_regs_odt;
uint16 control_regs_we_n;
uint32 control_regs_vref_dac_control;
uint16 wr_vdl_dqsp[SHMOO_AND28_BYTES_PER_INTERFACE];
uint16 wr_vdl_dqsn[SHMOO_AND28_BYTES_PER_INTERFACE];
uint16 wr_vdl_dq[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE];
uint16 wr_vdl_dm[SHMOO_AND28_BYTES_PER_INTERFACE];
uint16 wr_vdl_edc[SHMOO_AND28_BYTES_PER_INTERFACE];
uint8 wr_chan_dly_cyc[SHMOO_AND28_BYTES_PER_INTERFACE];
uint16 rd_vdl_dqsp[SHMOO_AND28_BYTES_PER_INTERFACE];
uint16 rd_vdl_dqsn[SHMOO_AND28_BYTES_PER_INTERFACE];
uint16 rd_vdl_dqp[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE];
uint16 rd_vdl_dqn[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE];
uint16 rd_vdl_dmp[SHMOO_AND28_BYTES_PER_INTERFACE];
uint16 rd_vdl_dmn[SHMOO_AND28_BYTES_PER_INTERFACE];
uint16 rd_en_vdl_cs[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_PHY_NOF_CS];
uint16 rd_en_dly_cyc[SHMOO_AND28_BYTES_PER_INTERFACE];
uint8 rd_control[SHMOO_AND28_BYTES_PER_INTERFACE];
} and28_shmoo_config_param_t;
typedef struct and28_vendor_info_s {
uint32 dram_density;
uint32 fifo_depth;
uint32 revision_id;
uint32 manufacture_id;
} and28_vendor_info_t;
typedef struct and28_shmoo_container_s {
uint32 sizeX;
uint32 sizeY;
uint32 yCapMin;
uint32 yCapMax;
uint32 yJump;
uint32 calibMode;
uint32 calibPos;
uint32 calibStart;
uint32 result2D[(SHMOO_AND28_RESULT2D_X)*(SHMOO_AND28_RESULT2D_Y)];
uint32 resultData[SHMOO_AND28_WORD];
uint32 shmooType;
uint32 dramType;
uint32 ctlType;
uint32 trefi;
uint32 step1000;
uint32 size1000UI;
uint32 endUI[SHMOO_AND28_MAX_VISIBLE_UI_COUNT];
uint32 engageUIshift;
uint32 wckInv;
} and28_shmoo_container_t;
typedef struct and28_step_size_s {
uint32 step1000;
uint32 size1000UI;
} and28_step_size_t;
typedef struct and28_ui_position_s {
uint32 ui;
uint32 position;
} and28_ui_position_t;
typedef uint32 and28_shmoo_error_array_t[SHMOO_AND28_ERROR_ARRAY_LENGTH];
int soc_and28_shmoo_dram_info_set(int unit, and28_shmoo_dram_info_t *sdi);
int soc_and28_shmoo_phy_init(int unit, int phy_ndx);
int soc_and28_shmoo_ctl(int unit, int phy_ndx, int shmoo_type, int stat,
int plot, int action, and28_shmoo_config_param_t *config_param);
#endif /* __SOC_BROADCOM_CYGNUS_SHMOO_AND28_H__ */
|
