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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
// Use simple device model for this file even in ramstage
#define __SIMPLE_DEVICE__
#include <arch/io.h>
#include <reset.h>
#define HT_INIT_CONTROL 0x6C
#define HTIC_BIOSR_Detect (1 << 5)
static void set_bios_reset(void)
{
u32 htic;
htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
htic &= ~HTIC_BIOSR_Detect;
pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
}
void do_hard_reset(void)
{
set_bios_reset();
/* Try rebooting through port 0xcf9 */
/*
* Actually it is not a real hard_reset
* --- it only reset coherent link table,
* but not reset link freq and width
*/
outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
}
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