1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
|
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __PICASSO_CHIP_H__
#define __PICASSO_CHIP_H__
#include <stddef.h>
#include <stdint.h>
#include <amdblocks/chip.h>
#include <commonlib/helpers.h>
#include <drivers/i2c/designware/dw_i2c.h>
#include <soc/i2c.h>
#include <soc/iomap.h>
#include <soc/southbridge.h>
#include <acpi/acpi_device.h>
#include <arch/x86/include/arch/smp/mpspec.h> /* point from top level */
/*
USB 2.0 PHY Parameters
*/
struct usb2_phy_tune {
/* Disconnect Threshold Adjustment. Range 0 - 0x7 */
uint8_t com_pds_tune;
/* Squelch Threshold Adjustment. Range 0 - 0x7 */
uint8_t sq_rx_tune;
/* FS/LS Source Impedance Adjustment. Range 0 - 0xF */
uint8_t tx_fsls_tune;
/* HS Transmitter Pre-Emphasis Curent Control. Range 0 - 0x3 */
uint8_t tx_pre_emp_amp_tune;
/* HS Transmitter Pre-Emphasis Duration Control. Range: 0 - 0x1 */
uint8_t tx_pre_emp_pulse_tune;
/* HS Transmitter Rise/Fall Time Adjustment. Range: 0 - 0x3 */
uint8_t tx_rise_tune;
/* HS DC Voltage Level Adjustment. Range 0 - 0xF */
uint8_t rx_vref_tune;
/* Transmitter High-Speed Crossover Adjustment. Range 0 - 0x3 */
uint8_t tx_hsxv_tune;
/* USB Source Impedance Adjustment. Range 0 - 0x3. */
uint8_t tx_res_tune;
};
struct soc_amd_picasso_config {
struct soc_amd_common_config common_config;
/*
* If sb_reset_i2c_slaves() is called, this devicetree register
* defines which I2C SCL will be toggled 9 times at 100 KHz.
* For example, should we need I2C0 and I2C3 have their slave
* devices reseted by toggling SCL, use:
*
* register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL)
*/
u8 i2c_scl_reset;
struct dw_i2c_bus_config i2c[I2C_MASTER_DEV_COUNT];
enum {
I2S_PINS_MAX_HDA = 0, /* HDA w/reset 3xSDI, SW w/Data0 */
I2S_PINS_MAX_MHDA = 1, /* HDA no reset 3xSDI, SW w/Data0-1 */
I2S_PINS_MIN_HDA = 2, /* HDA w/reset 1xSDI, SW w/Data0-2 */
I2S_PINS_MIN_MHDA = 3, /* HDA no reset 1xSDI, SW w/Data0-3 */
I2S_PINS_I2S_TDM = 4,
I2S_PINS_UNCONF = 7, /* All pads will be input mode */
} acp_pin_cfg;
/**
* IRQ 0 - 15 have a default trigger of edge and default polarity of high.
* If you have a device that requires a different configuration you can override the
* settings here.
*/
struct {
uint8_t irq;
/* See MP_IRQ_* from mpspec.h */
uint8_t flags;
} irq_override[16];
/* DMIC select GPIO for I2S machine driver AMDI5682 */
struct acpi_gpio dmic_select_gpio;
/* Options for these are in src/arch/x86/include/acpi/acpi.h */
uint16_t fadt_boot_arch;
uint32_t fadt_flags;
/* System config index */
uint8_t system_config;
/* STAPM Configuration */
uint32_t fast_ppt_limit;
uint32_t slow_ppt_limit;
uint32_t slow_ppt_time_constant;
uint32_t stapm_time_constant;
uint32_t sustained_power_limit;
/* PROCHOT_L de-assertion Ramp Time */
uint32_t prochot_l_deassertion_ramp_time;
/* Lower die temperature limit */
uint32_t thermctl_limit;
/* FP5 Processor Voltage Supply PSI Currents. 0 indicates use SOC default */
uint32_t psi0_current_limit;
uint32_t psi0_soc_current_limit;
uint32_t vddcr_soc_voltage_margin;
uint32_t vddcr_vdd_voltage_margin;
/* VRM Limits. 0 indicates use SOC default */
uint32_t vrm_maximum_current_limit;
uint32_t vrm_soc_maximum_current_limit;
uint32_t vrm_current_limit;
uint32_t vrm_soc_current_limit;
/* Misc SMU settings */
uint8_t sb_tsi_alert_comparator_mode_en;
uint8_t core_dldo_bypass;
uint8_t min_soc_vid_offset;
uint8_t aclk_dpm0_freq_400MHz;
uint32_t telemetry_vddcr_vdd_slope;
uint32_t telemetry_vddcr_vdd_offset;
uint32_t telemetry_vddcr_soc_slope;
uint32_t telemetry_vddcr_soc_offset;
enum {
SD_EMMC_DISABLE,
SD_EMMC_SD_LOW_SPEED,
SD_EMMC_SD_HIGH_SPEED,
SD_EMMC_SD_UHS_I_SDR_50,
SD_EMMC_SD_UHS_I_DDR_50,
SD_EMMC_SD_UHS_I_SDR_104,
SD_EMMC_EMMC_SDR_26,
SD_EMMC_EMMC_SDR_52,
SD_EMMC_EMMC_DDR_52,
SD_EMMC_EMMC_HS200,
SD_EMMC_EMMC_HS400,
SD_EMMC_EMMC_HS300,
} sd_emmc_config;
uint8_t xhci0_force_gen1;
struct usb2_phy_tune usb_2_port_0_tune_params;
struct usb2_phy_tune usb_2_port_1_tune_params;
struct usb2_phy_tune usb_2_port_2_tune_params;
struct usb2_phy_tune usb_2_port_3_tune_params;
struct usb2_phy_tune usb_2_port_4_tune_params;
struct usb2_phy_tune usb_2_port_5_tune_params;
};
typedef struct soc_amd_picasso_config config_t;
extern struct device_operations pci_domain_ops;
#endif /* __PICASSO_CHIP_H__ */
|
