1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
|
/* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <drivers/i2c/designware/dw_i2c.h>
#include <soc/acpi.h>
#include <soc/cpu.h>
#include <soc/data_fabric.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/southbridge.h>
#include "chip.h"
#include <fsp/api.h>
/* Supplied by i2c.c */
extern struct device_operations picasso_i2c_mmio_ops;
/* Supplied by uart.c */
extern struct device_operations picasso_uart_mmio_ops;
struct device_operations cpu_bus_ops = {
.read_resources = noop_read_resources,
.set_resources = noop_set_resources,
.init = mp_cpu_bus_init,
.acpi_fill_ssdt = generate_cpu_entries,
};
const char *soc_acpi_name(const struct device *dev)
{
if (dev->path.type == DEVICE_PATH_DOMAIN)
return "PCI0";
if (dev->path.type == DEVICE_PATH_USB) {
switch (dev->path.usb.port_type) {
case 0:
/* Root Hub */
return "RHUB";
case 3:
/* USB3 ports */
switch (dev->path.usb.port_id) {
case 0: return "SS01";
case 1: return "SS02";
case 2: return "SS03";
}
break;
}
return NULL;
}
if (dev->path.type != DEVICE_PATH_PCI)
return NULL;
if (dev->bus->dev->path.type == DEVICE_PATH_DOMAIN) {
switch (dev->path.pci.devfn) {
case GNB_DEVFN:
return "GNB";
case IOMMU_DEVFN:
return "IOMM";
case PCIE_GPP_0_DEVFN:
return "PBR0";
case PCIE_GPP_1_DEVFN:
return "PBR1";
case PCIE_GPP_2_DEVFN:
return "PBR2";
case PCIE_GPP_3_DEVFN:
return "PBR3";
case PCIE_GPP_4_DEVFN:
return "PBR4";
case PCIE_GPP_5_DEVFN:
return "PBR5";
case PCIE_GPP_6_DEVFN:
return "PBR6";
case PCIE_GPP_A_DEVFN:
return "PBRA";
case PCIE_GPP_B_DEVFN:
return "PBRB";
case LPC_DEVFN:
return "LPCB";
case SMBUS_DEVFN:
return "SBUS";
default:
printk(BIOS_WARNING, "Unknown root PCI device: dev: %d, fn: %d\n",
PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
return NULL;
}
}
if (dev->bus->dev->path.type == DEVICE_PATH_PCI
&& dev->bus->dev->path.pci.devfn == PCIE_GPP_A_DEVFN) {
switch (dev->path.pci.devfn) {
case XHCI0_DEVFN:
return "XHC0";
case XHCI1_DEVFN:
return "XHC1";
default:
printk(BIOS_WARNING, "Unknown Bus A PCI device: dev: %d, fn: %d\n",
PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
return NULL;
}
}
printk(BIOS_WARNING, "Unknown PCI device: dev: %d, fn: %d\n",
PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
return NULL;
};
struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
.scan_bus = pci_domain_scan_bus,
.acpi_name = soc_acpi_name,
};
static struct device_operations pci_ops_ops_bus_ab = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,
.scan_bus = pci_scan_bridge,
.reset_bus = pci_bus_reset,
.acpi_fill_ssdt = acpi_device_write_pci_dev,
};
static void set_mmio_dev_ops(struct device *dev)
{
switch (dev->path.mmio.addr) {
case APU_I2C2_BASE:
case APU_I2C3_BASE:
case APU_I2C4_BASE:
dev->ops = &picasso_i2c_mmio_ops;
break;
case APU_UART0_BASE:
case APU_UART1_BASE:
case APU_UART2_BASE:
case APU_UART3_BASE:
dev->ops = &picasso_uart_mmio_ops;
break;
}
}
static void enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
dev->ops = &cpu_bus_ops;
} else if (dev->path.type == DEVICE_PATH_PCI) {
if (dev->bus->dev->path.type == DEVICE_PATH_DOMAIN) {
switch (dev->path.pci.devfn) {
case PCIE_GPP_A_DEVFN:
case PCIE_GPP_B_DEVFN:
dev->ops = &pci_ops_ops_bus_ab;
}
}
sb_enable(dev);
} else if (dev->path.type == DEVICE_PATH_MMIO) {
set_mmio_dev_ops(dev);
}
}
static void soc_init(void *chip_info)
{
default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables;
fsp_silicon_init(acpi_is_wakeup_s3());
data_fabric_set_mmio_np();
southbridge_init(chip_info);
}
static void soc_final(void *chip_info)
{
southbridge_final(chip_info);
}
struct chip_operations soc_amd_picasso_ops = {
CHIP_NAME("AMD Picasso SOC")
.enable_dev = enable_dev,
.init = soc_init,
.final = soc_final
};
|
