blob: 30cbdcb81ad36b4cf00775c0c04a9bc18a6a1de8 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
|
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
#include <amdblocks/amd_pci_mmconf.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
void enable_pci_mmconf(void)
{
msr_t mmconf;
mmconf.hi = 0;
mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN
| fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT;
wrmsr(MMIO_CONF_BASE, mmconf);
}
|