blob: 5d3e13b1a25a394def96df9f99278e9cc76da579 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
.code32
#include <cpu/x86/cr.h>
.globl ap_teardown_car
ap_teardown_car:
pop %esi /* return address, don't care */
pop %esi /* flags */
/* chipset_teardown_car() is expected to disable cache-as-ram. */
call chipset_teardown_car
/*
* Check flags requirements (0 = FALSE, 1 = TRUE) :
* bit 0 = ExecWbinvd
* bit 1 = CacheEn
*/
/*
* TODO: Either use or remove this code - we'll node if the code
* is needed when 3 conditions happens:
* 1) This code is in place
* 2) AGESA code that calls HALT_THIS_AP is in place
* 3) We boot to OS, go to S3 and resume.
* If S3 resume fails, this code might be needed, if S3 resume
* is successful then the code can be removed.
*/
/*
* Commented out until defined if needed or not.
* test %esi, 1
* jz 1f
* wbinvd
* 1:
*/
test %esi, 2
jz 2f
/* Enable cache */
mov %cr0, %eax
and $(~(CR0_CD | CR0_NW)), %eax
mov %eax, %cr0
2:
cli
hlt
jmp 2b
|