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config SOC_AMD_COMMON_BLOCK_CAR
bool
default n
help
This option allows the SOC to use a standard AMD cache-as-ram (CAR)
implementation. CAR setup is built into bootblock and teardown is
in postcar. The teardown procedure does not preserve the stack so
it may not be appropriate for a romstage implementation without
additional consideration. If this option is not used, the SOC must
implement these functions separately.
This is only used for AMD CPU before family 17h. From family 17h on
the RAM is already initialized by the PSP before the x86 cores are
released from reset.
config SOC_AMD_COMMON_BLOCK_NONCAR
bool
default n
help
From family 17h on AMD CPUs/APUs don't use cache as RAM (CAR) any
more, since the RAM initialization is already done by the PSP when
the x86 cores are released from reset.
if SOC_AMD_COMMON_BLOCK_NONCAR
config MEMLAYOUT_LD_FILE
string
default "src/soc/amd/common/block/cpu/noncar/memlayout.ld"
endif # SOC_AMD_COMMON_BLOCK_NONCAR
config SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
bool
select COLLECT_TIMESTAMPS_NO_TSC # selected use SoC-specific timestamp function
select TSC_SYNC_LFENCE
select UDELAY_TSC
default n
help
Select this option to add the common functions for getting the TSC
frequency of AMD family 17h and 19h CPUs/APUs and to provide TSC-
based monotonic timer functionality to the build.
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