blob: ffd56de66d40db0471c4095847b73c510f2a465e (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
|
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/device.h>
#include <fsp/api.h>
#include <soc/southbridge.h>
#include <types.h>
#include "chip.h"
/* Supplied by uart.c */
extern struct device_operations cezanne_uart_mmio_ops;
struct device_operations cpu_bus_ops = {
.read_resources = noop_read_resources,
.set_resources = noop_set_resources,
.init = mp_cpu_bus_init,
};
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
.scan_bus = pci_domain_scan_bus,
};
static void set_mmio_dev_ops(struct device *dev)
{
switch (dev->path.mmio.addr) {
case APU_UART0_BASE:
case APU_UART1_BASE:
dev->ops = &cezanne_uart_mmio_ops;
break;
}
}
static void enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
switch (dev->path.type) {
case DEVICE_PATH_DOMAIN:
dev->ops = &pci_domain_ops;
break;
case DEVICE_PATH_CPU_CLUSTER:
dev->ops = &cpu_bus_ops;
break;
case DEVICE_PATH_MMIO:
set_mmio_dev_ops(dev);
break;
default:
break;
}
}
static void soc_init(void *chip_info)
{
fsp_silicon_init();
fch_init(chip_info);
}
static void soc_final(void *chip_info)
{
fch_final(chip_info);
}
struct chip_operations soc_amd_cezanne_ops = {
CHIP_NAME("AMD Cezanne SoC")
.enable_dev = enable_dev,
.init = soc_init,
.final = soc_final
};
|
