1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* The socket type Fr2, G (1207) are not tested.
*/
static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload,
u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL,
u8 *CMDmode);
void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, u32 dct)
{
Get_ChannelPS_Cfg0_D(pDCTstat->MAdimms[dct], pDCTstat->Speed,
pDCTstat->MAload[dct], pDCTstat->DATAload[dct],
&(pDCTstat->CH_ADDR_TMG[dct]), &(pDCTstat->CH_ODC_CTL[dct]),
&pDCTstat->_2Tmode);
if (pDCTstat->GangedMode == 1 && dct == 0)
Get_ChannelPS_Cfg0_D(pDCTstat->MAdimms[1], pDCTstat->Speed,
pDCTstat->MAload[1], pDCTstat->DATAload[1],
&(pDCTstat->CH_ADDR_TMG[1]), &(pDCTstat->CH_ODC_CTL[1]),
&pDCTstat->_2Tmode);
pDCTstat->CH_EccDQSLike[0] = 0x0302;
pDCTstat->CH_EccDQSLike[1] = 0x0302;
}
/*
* In: MAAdimms - number of DIMMs on the channel
* : Speed - Speed (see DCTStatstruc.Speed for definition)
* : MAAload - number of address bus loads on the channel
* : DATAAload - number of ranks on the channel
* Out: AddrTmgCTL - Address Timing Control Register Value
* : ODC_CTL - Output Driver Compensation Control Register Value
* : CMDmode - CMD mode
*/
static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload,
u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL,
u8 *CMDmode)
{
*AddrTmgCTL = 0;
*ODC_CTL = 0;
*CMDmode = 1;
if (mctGet_NVbits(NV_MAX_DIMMS) == 4) {
if (Speed == 4) {
*AddrTmgCTL = 0x00000000;
} else if (Speed == 5) {
*AddrTmgCTL = 0x003C3C3C;
if (MAAdimms > 1)
*AddrTmgCTL = 0x003A3C3A;
} else if (Speed == 6) {
if (MAAdimms == 1)
*AddrTmgCTL = 0x003A3A3A;
else
*AddrTmgCTL = 0x00383A38;
} else {
if (MAAdimms == 1)
*AddrTmgCTL = 0x00373937;
else
*AddrTmgCTL = 0x00353935;
}
} else {
if (Speed == 4) {
*AddrTmgCTL = 0x00000000;
if (MAAdimms == 3)
*AddrTmgCTL = 0x00380038;
} else if (Speed == 5) {
if (MAAdimms == 1)
*AddrTmgCTL = 0x003C3C3C;
else if (MAAdimms == 2)
*AddrTmgCTL = 0x003A3C3A;
else
*AddrTmgCTL = 0x00373C37;
} else if (Speed == 6) {
if (MAAdimms == 1)
*AddrTmgCTL = 0x003A3A3A;
else if (MAAdimms == 2)
*AddrTmgCTL = 0x00383A38;
else
*AddrTmgCTL = 0x00343A34;
} else {
if (MAAdimms == 1)
*AddrTmgCTL = 0x00393939;
else if (MAAdimms == 2)
*AddrTmgCTL = 0x00363936;
else
*AddrTmgCTL = 0x00303930;
}
}
if ((MAAdimms == 1) && (MAAload < 4))
*ODC_CTL = 0x20113222;
else
*ODC_CTL = 0x20223222;
*CMDmode = 1;
}
|
