1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
|
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Note: Only need HID on Primary Bus */
External (TOM1)
External (TOM2)
Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
/* Describe the Northbridge devices */
Device(AMRT) {
Name(_ADR, 0x00000000)
} /* end AMRT */
/* The internal GFX bridge */
Device(AGPB) {
Name(_ADR, 0x00010000)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD) { Return(APR1) } /* APIC mode */
Return (PR1) /* PIC Mode */
}
} /* end AGPB */
/* The internal GFX bridge */
Device(HDMI) {
Name(_ADR, 0x00010001)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD) { Return(APR1) } /* APIC mode */
Return (PR1) /* PIC Mode */
}
} /* end HDMI */
/* Dev 2 & 3 are external GFX bridges, not used in Family14 */
/* Dev4 GPP0 Root Port Bridge */
Device(PBR4) {
Name(_ADR, 0x00040000)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD) { Return(APS4) } /* APIC mode */
Return (PS4) /* PIC Mode */
} /* end _PRT */
} /* end PBR4 */
/* Dev5 GPP1 Root Port Bridge */
Device(PBR5) {
Name(_ADR, 0x00050000)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD) { Return(APS5) } /* APIC mode */
Return (PS5) /* PIC Mode */
} /* end _PRT */
} /* end PBR5 */
/* Dev6 GPP2 Root Port Bridge */
Device(PBR6) {
Name(_ADR, 0x00060000)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD) { Return(APS6) } /* APIC mode */
Return (PS6) /* PIC Mode */
} /* end _PRT */
} /* end PBR6 */
/* The onboard EtherNet chip */
Device(PBR7) {
Name(_ADR, 0x00070000)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD) { Return(APS7) } /* APIC mode */
Return (PS7) /* PIC Mode */
} /* end _PRT */
} /* end PBR7 */
Device(PE20) {
Name(_ADR, 0x00150000)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD) { Return(APE0) } /* APIC mode */
Return (PE0) /* PIC Mode */
} /* end _PRT */
} /* end PE20 */
Device(PE21) {
Name(_ADR, 0x00150001)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD) { Return(APE1) } /* APIC mode */
Return (PE1) /* PIC Mode */
} /* end _PRT */
} /* end PE21 */
Device(PE22) {
Name(_ADR, 0x00150002)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD) { Return(APE2) } /* APIC mode */
Return (APE2) /* PIC Mode */
} /* end _PRT */
} /* end PE22 */
Device(PE23) {
Name(_ADR, 0x00150003)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD) { Return(APE3) } /* APIC mode */
Return (PE3) /* PIC Mode */
} /* end _PRT */
} /* end PE23 */
/* Northbridge function 3 */
Device(NBF3) {
Name(_ADR, 0x00180003)
/* k10temp thermal zone */
#include "thermal_mixin.asl"
} /* end NBF3 */
|
