aboutsummaryrefslogtreecommitdiff
path: root/src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts
blob: 454c3d807c5c9c9e6bd6de5a9068403aa272320b (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
/*
 * This file is part of the Linux kernel.
 *
 * Copyright (c) 2018-2019 SiFive, Inc
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/include/ "fu540-c000.dtsi"

/ {
	#address-cells = <2>;
	#size-cells = <2>;
	model = "SiFive HiFive Unleashed A00";
	compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";

	chosen {
	};

	cpus {
		/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
		timebase-frequency = <1000000>;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x2 0x00000000>;
	};

	soc {
	};

	hfclk: hfclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <33333333>;
		clock-output-names = "hfclk";
	};

	rtcclk: rtcclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <1000000>;
		clock-output-names = "rtcclk";
	};
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&i2c0 {
	status = "okay";
};

&qspi0 {
	status = "okay";
	flash@0 {
		compatible = "issi,is25wp256", "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <50000000>;
		m25p,fast-read;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
	};
};

&qspi2 {
	status = "okay";
	mmc@0 {
		compatible = "mmc-spi-slot";
		reg = <0>;
		spi-max-frequency = <20000000>;
		voltage-ranges = <3300 3300>;
		disable-wp;
	};
};

&eth0 {
	status = "okay";
	phy-mode = "gmii";
	phy-handle = <&phy0>;
	phy0: ethernet-phy@0 {
		reg = <0>;
	};
};