1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
|
/* SPDX-License-Identifier: GPL-2.0-only */
#include <option.h>
#include <soc/cnl_memcfg_init.h>
#include <soc/gpio.h>
#include <soc/romstage.h>
#include <variant.h>
#include <variant/gpio.h>
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
uint8_t vtd = 1;
const struct cnl_mb_cfg cfg = {
.spd = {
[0] = { READ_SMBUS, { 0x50 << 1 } },
[2] = { READ_SMBUS, { 0x52 << 1 } },
},
.rcomp_resistor = { 121, 75, 100 },
.rcomp_targets = { 50, 25, 20, 20, 26 },
.dq_pins_interleaved = 1,
.vref_ca_config = 2,
.ect = 0,
};
cannonlake_memcfg_init(&memupd->FspmConfig, &cfg);
memupd->FspmConfig.EccSupport = 1;
memupd->FspmConfig.UserBd = BOARD_TYPE_MOBILE;
get_option(&vtd, "vtd");
memupd->FspmTestConfig.VtdDisable = !vtd;
get_option(&memupd->FspmConfig.HyperThreading, "hyper_threading");
variant_romstage_params(memupd);
variant_configure_gpios();
}
__weak void variant_romstage_params(FSPM_UPD *const mupd)
{
}
|
