aboutsummaryrefslogtreecommitdiff
path: root/src/mainboard/scaleway/tagada/ramstage.c
blob: 55cd17562ed6ddd0eb8f987b0476358f8e0c9cdf (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
/*
 * This file is part of the coreboot project.
 *
 * Copyright (C) 2014 - 2017 Intel Corporation
 * Copyright (C) 2017 - 2018 Online SAS.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <console/console.h>
#include <fsp/api.h>
#include <soc/ramstage.h>

#include "bmcinfo.h"

void mainboard_silicon_init_params(FSPS_UPD *params)
{
	/* Disable eMMC */
	params->FspsConfig.PcdEnableEmmc = 0;

	if (bmcinfo_disable_nic1())
		params->FspsConfig.PcdEnableGbE = 2; // disable lan 1 only
}