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chip northbridge/intel/sandybridge
# IGD Displays
register "gfx" = "GMA_STATIC_DISPLAYS(0)"
# Enable DisplayPort Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
# Enable Panel as LVDS and configure power delays
register "gpu_panel_port_select" = "PANEL_PORT_LVDS"
register "gpu_panel_power_cycle_delay" = "5" # T4: 400ms
register "gpu_panel_power_up_delay" = "400" # T1+T2: 40ms
register "gpu_panel_power_down_delay" = "150" # T3: 15ms
register "gpu_panel_power_backlight_on_delay" = "2100" # T5: 210ms
register "gpu_panel_power_backlight_off_delay" = "2100" # TD: 210ms
# Set backlight PWM values
register "gpu_cpu_backlight" = "0x000001e8"
register "gpu_pch_backlight" = "0x03d00000"
register "ec_present" = "1"
register "max_mem_clock_mhz" = "666"
register "usb_port_config" = "{
{ 1, 0, 0x0080 },
{ 1, 1, 0x0080 },
{ 1, 0, 0x0040 },
{ 1, 0, 0x0040 },
{ 0, 0, 0x0000 },
{ 0, 0, 0x0000 },
{ 0, 0, 0x0000 },
{ 0, 0, 0x0000 },
{ 1, 4, 0x0040 },
{ 0, 4, 0x0000 },
{ 0, 4, 0x0000 },
{ 1, 4, 0x0040 },
{ 0, 4, 0x0000 },
{ 0, 4, 0x0000 },}"
device domain 0 on
subsystemid 0x1ae0 0xc000 inherit
device ref host_bridge on end # host bridge
device ref igd on end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "alt_gp_smi_en" = "0x0002"
register "gpi1_routing" = "1"
register "gpi7_routing" = "2"
register "sata_port_map" = "0x1"
# EC range is 0xa00-0xa3f
register "gen1_dec" = "0x003c0a01"
register "gen2_dec" = "0x003c0b01"
register "gen3_dec" = "0x00fc1601"
register "usb_port_config" = "{
{ 1, 1, 0 }, /* P0: Port 0 (OC0) */
{ 1, 1, 1 }, /* P1: Port 1 (OC1) */
{ 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */
{ 1, 0, -1 }, /* P3: MMC (no OC) */
{ 0, 0, -1 }, /* P4: Empty */
{ 0, 0, -1 }, /* P5: Empty */
{ 0, 0, -1 }, /* P6: Empty */
{ 0, 0, -1 }, /* P7: Empty */
{ 1, 0, -1 }, /* P8: MINIPCIE2 (no OC) */
{ 0, 0, -1 }, /* P9: Empty */
{ 0, 0, -1 }, /* P10: Empty */
{ 1, 0, -1 }, /* P11: Camera (no OC) */
{ 0, 0, -1 }, /* P12-13: Empty */
{ 0, 0, -1 }
}"
device ref mei1 on end # Management Engine Interface 1
device ref mei2 off end # Management Engine Interface 2
device ref me_ide_r off end # Management Engine IDE-R
device ref me_kt off end # Management Engine KT
device ref gbe off end # Intel Gigabit Ethernet
device ref ehci2 on end # USB2 EHCI #2
device ref hda on end # High Definition Audio
device ref pcie_rp1 on end # PCIe Port #1 (WLAN)
device ref pcie_rp2 off end # PCIe Port #2
device ref pcie_rp3 off end # PCIe Port #3
device ref pcie_rp4 on end # PCIe Port #4 (LAN)
device ref pcie_rp5 off end # PCIe Port #5
device ref pcie_rp6 off end # PCIe Port #6
device ref pcie_rp7 off end # PCIe Port #7
device ref pcie_rp8 off end # PCIe Port #8
device ref ehci1 on end # USB2 EHCI #1
device ref pci_bridge off end # PCI bridge
device ref lpc on # LPC bridge
chip superio/smsc/mec1308
device pnp 2e.1 on # PM1
io 0x60 = 0xb00
end
device pnp 2e.2 off end # EC1
device pnp 2e.3 off end # EC2
device pnp 2e.4 off end # UART
device pnp 2e.7 on # KBC
irq 0x70 = 1
end
device pnp 2e.8 on # EC0
io 0x60 = 0x62
end
device pnp 2e.9 on # MBX
io 0x60 = 0xa00
end
end
chip ec/smsc/mec1308
register "mailbox_port" = "0xa00"
device pnp ff.1 off end
end
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end
device ref sata1 on end # SATA Controller 1
device ref smbus on
subsystemid 0x18D1 0x04B4
end # SMBus
device ref sata2 off end # SATA Controller 2
device ref thermal on end # Thermal
end
end
end
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