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chip soc/intel/broadwell
# Port 0 is HDD
# Port 3 is M.2 NGFF
register "sata_port_map" = "0x9"
# Port tuning for link stability
register "sata_port0_gen3_dtle" = "9"
register "sata_port3_gen3_dtle" = "9"
device domain 0 on
device pci 1c.2 on end # PCIe Port #3 - LAN
end
end
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